PCIe Hard IP Configuration Question

[Altera_Forum]

I'm simulating the SOPC variation of the testbench that the PCIe Compiler creates so that I can see how the BFM is configuring the PCIe IP. I see several testbench messages like "INFO: 37192 ns EP PCI Express Device Control Register (0010)" that tell me the RP has accessed the EP Control Register space but I don't see any activity on the Avalon MM Bus signals. When I get to the point in the testbench where the memory is being accessed I again see testbench messages that this is happening and then I do see Avalon MM Bus signal activity. Why don't I see any Avalon Bus activity during the configuration?

[Altera_Forum]

I'm in the process of sim'ing the PCIe hard IP. Which .do script are you running? Are you using ModelSim-AE?

[Altera_Forum]

I'm running ModelSim 6.5d. If you are doing an SOPC design there will be a setup_sim.do. This creates some aliases like c, s, w.. I had some issues with this flow compiling all of the Altera libs into my work lib. It takes a very long time. There are some ways to speed it up..