PCIe P-Tile Flow Control

[anat]

Hi Team,
In the PCIe P-Tile TX flow control, user guide says "internally generated TLPs also consume FC credits" Page 72. My questions are 
1.How does the user application know how muche credits consumed internally?
2.What will be the impact of this internal unit consumtion on the TDM tx_cdts_limit_o interface, should we expect a decrease in credits, or advertized credits remains same?
3. Can the PCIe IP manage this internal credits consumption or the user application should account this as well while calculating the available credits?

4.In the case of RX flow control, instead of the number of credits, flow control is defined in terms of Number of TLPs. Any examples for this conversion while calculating available credits?

[Wincent_Altera · Accepted solution]

Hi Anat,

On P-tile IP, there is no handling required by user application when credit is consumed due to internally generated TLP. Just that the credit return to user is slower.

This means that HIP decrements new FC_update credits values before to pass them to the user application as TX credit limit when HIP has consumed internal credits.

In that sense user application will have less credits that once sent by PCIe link partner agent in FC_update DLLP.

For example, the RP send FC_update PD=20 and HIP had consumed 4 credits then user application will received PD=16 (TX credit limit signal) where previous TX credit limit value was PD=16 or less.

Does this acceptably answer your question?

Regards,

Wincent

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Altera

[anat]

Hi Wincent - Thank you. 
Could you clarify on the RX side FC as well, 

"4.In the case of RX flow control, instead of the number of credits, flow control is defined in terms of Number of TLPs. Any examples for this conversion while calculating available credits?"

[Wincent_Altera]

Hi,

in Rx flow control, perhaps you can check on 
https://www.intel.com/content/www/us/en/docs/programmable/683059/24-3/rx-flow-control-interface.html

Let me know if there is anything in the user guide that is not clear for you, or I am not answering your question accurately.

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

Regards,

Wincent_Altera

[anat]

Hi,

How to advertize infinite credits for RX interface for CPL?

[Wincent_Altera]

Hi ,

The information for infinite credits for CPL, you may refer to

https://www.intel.com/content/www/us/en/docs/programmable/683059/24-3/completion-buffer-size.html

Regards,
Wincent_Altera

[anat]

Hi,
This section does not explain completion buffer size with respect to rx flow control interface. My question is, I need to advertize infinite credits for RX CPL, then what is the value I should transfer in the "rx_buffer_limit_i[11:0]" interface. I'm using Gen4 1x8 mode.

[Wincent_Altera]

Hi,

Please allow me to have sometime to check on your queries in previous reply.

Will get back to you once I found any related information.

Regards,

Wincent_Altera

[anat]

Any updates?

[Wincent_Altera]

Hi ,

I still checking with our design team, it might take sometime.
I will raise this ticket level as top priority, hope can get the feedback soon.

Sorry for keep you waiting.

Regards,
Wincent_Altera

[Wincent_Altera]

Hi Anat, 

Sorry for keep you waiting.
If for R-tile , there is features where user can sends a value of zero on the rx_buffer_limit_i during CPL timeslot.
BUT, for P-tile those features is not available.

But, CPL credit advertised to the link partner by P tile during flow control initialization is infinite if refer to the user guide

value passed by the rx_buffer_limit* interface signal will not affect the value of credit advertised by the HIP to the link partner, the Hip will only initialize credit to the link partner according to the value in the screenshot above, and periodically advertise the credit to the link partner in accordance with the TLP received. 

Hope that clarified.

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Altera

[anat]

Hi Wincent, 
From your explanation, I understand
a. P-Tile HIP advertise infinite credite for CPL during initialization.
b. Value passed by the rx_buffer_limit* interface signal will not affect the value of credit advertised.

if this interface doesn't affect the credit advertised what is the actual use of this rx_buffer_limit* interface? 

[Wincent_Altera]

Hi Anat,

a. P-Tile HIP advertise infinite credite for CPL during initialization.
>> Yes, for P-tile, CPL credit is advertised as infinete
b. Value passed by the rx_buffer_limit* interface signal will not affect the value of credit advertised.
>> Yes, that is right  Hip will only initialize credit to the link partner according to the value in the screenshot above (p-tile), and periodically advertise the credit to the link partner in accordance with the TLP received

Hope that clarified.

Regards,
Wincent_Altera

[anat]

Hi,

"if this interface doesn't affect the credit advertised what is the actual use of this rx_buffer_limit* interface?" --- Please clarify this as well

[Wincent_Altera]

Hi Anat,

RX flow control interface provides information on the application's available RX buffer space to the PCIe Hard IP in a time-division multiplexing (TDM) manner. It reports the space available in number of TLPs.

The RX flow control interface is optional and disabled by default in the IP GUI. If disabled, it indicates that there is no limit in the application RX buffer space.

Hope this clarified.

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this IPS case.

Do you have any further questions on this matter ?

Else do I have your permission to close this forum ticket ?

Regards,

Wincent_Altera

[anat]

Thanks. Please close

[Wincent_Altera]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have new question, please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of ddesire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.

Regards,
Wincent_Altera