PCIe pld_clk conflicting coreclkout statements

[corestar]

I'm using a Cyclone V GT with PCIe ST core. The app works fine when I drive pld_clk with coreclockout, but fails when I drive pld_clk with a 150 MHz external clock. I used 150 MHz instead of 125 MHz since it says you must use a 0 ppm accuracy clock at 125 MHz and I don't know how to do that!

According to "Cyclone V Streaming Interface for PCIe Solutions User Guide", I should be able to do this (Table 4-5):

But according to "Cyclone V Hard IP for PCI Express User Guide":

This seems contradictory. And the latter seems wrong since if you must drive it with coreclkout, why did they not just do that internally?  

So can I drive pld_clk from a PLL? This would save alot of clock domain crossing inside my App.

[ventt]

Hi @corestar,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with findings.

Thanks.

Best Regards,

VenTingT

[ventt]

Hi @corestar,

We would recommend users drive the pld_clk with coreclkout_hip.

If you wish to drive the pld_clk at a higher speed, it is recommended to do it in the user logic in the application layer but not directly to the FPGA.

Regarding the pld_clk signal description of the two documents, I'm checking it with the internal team. It will take some time for the checking.

Thanks.

Best Regards,

VenTingT

[corestar]

Hello @ventt 

My main motivation was avoiding a few clock domain crossings as opposed to higher clock speed.

Since the design works fine when I drive pld_clk with coreclockout_hip, but fails otherwise, I have to assume it is a requirement. But the first guide mentioned went into great detail on the nature of the external clock, so it seemed like they knew what they were talking about.

It will be interesting to here the resolution.

Thanks,

[ventt · Accepted solution]

Hi @corestar,

Thanks for sharing your objective.

My apologies for the delayed response, I took some time to gather the information.

In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.

In the situation that you wish to drive the pld_clk with an other clock source, the following clock frequencies of the clock source could be used:

1.When coreclkout_hip is 62.5 MHz:

Try to use 125 MHz, or 250 MHz.

2. When coreclkout_hip is 125 MHz:

Try to use 250 MHz.

Please note that not all frequencies of other clock source within the specified range can be used to drive the pld_clk.

Thanks.

Best Regards,

VenTingT

[corestar]

Hello @ventt 

Thanks for the info. So apparently both documents are in error. You can use an external clock, but not in the range specified. The 150 MHz should have worked according to the second one. I don't think I could meet timing at 250 Mhz. They may want to update the documentation.

You mention:

In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.

It actually complicates timing for the Application layer, so I assume you mean it simplifies it for the PCIe core?

In any event, the safest solution is clearly to drive pld_clk with coreclockout_hip. It works.

Might as well close this one.

Regards,

Dave

[ventt]

Hi @corestar,

Thank you for your feedback. I will forward it to our internal team for review and necessary updates to the documentation.

I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

VenTingT

p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate 4/5 for the survey.