PCie SRNS, separate perstn

[sambkr]

Dear Support, 

I plan to use a PCie switch board to connect a x16 pcie lane inside a PC to 4 FPGA (4 lanes pcie) cyclone 10 GX boards.

FPGA boards will be endpoints.

The Pcie switch board use mini sas HD cables (Active Optical Cable). 1 cable by target board.

I only have the Rx and Tx typicall PCie signals inside the cable.

For the Pcie refclk, I will be in SRNS that seems supported by Pcie IP.

How to deal with perstn ?

I'am used to work with common refclk and persnt, but unfortunatelly these signal not passed through the active cable (SFF-8644).

For sure I can generate a nrst signal for example when the fpga power supply is OK (don't know if it can work) but how to deal if I get PC reboot, for new enumeration and link training.

I read something about Hot reset or in band reset. 

Do I have something to do to use it ? 

Is it supported when used GEN 2 with cyclone 10 GX IP ? 

Any other ideas to have it working ? 

Best regards.

[wchiah]

Hi,

Are you using any design example provided in the IP catalog ?

Or that is a custom design ?

If you are using AVST design, you may refer to

https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/reset-status-and-link-training-signals-reset.html

it got explain about the reset signal.

If you would like to use the hard reset pin, I would say the nCONFIG pin is the most accurate pin for you. It is a dedicated configuration control input pin where pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level initiates reconfiguration.

Regards,

Wincent_Intel

[sambkr]

Hi, 

I will use AVMM ref design concerning pcie IP. 

Configured GEN2 x4 with DMA.

I don't really get my answer reading your post.

The Pcie switch bord into the will use some PLX Switch, switching 1 x16 lanes into 4 (x4) lanes. 

I catch you about connecting hard Ip Pcie reset with nconfig signal.

Could you confirm if the PC reboot, the FPGA PCie IP is able to handle In band reset, and able to reset LTSSM for new link training and enumeration ? 

For my test I plan to use the cyclone 10 GX devKit (DK-DEV-10CX220-A), with some custom board to convert from SFF-8644 to PCie riser.

Best regards.

[wchiah]

Hi,

As what I know, in-band reset is not used during the link training and enumeration process in PCIe.

The primary purpose of in-band reset is to reset the internal state of a PCIe device without disrupting the communication link. It allows the device to recover from certain error conditions or reset specific functions while maintaining the link with other devices.

During link training and enumeration, the LTSSM (Link Training and Status State Machine) follows a specific protocol defined by the PCIe specification. The LTSSM handles the negotiation and establishment of the link between devices, including the training of the communication parameters such as link width, speed, and other features.

The link training process involves a sequence of states and transitions as defined by the PCIe specification. It relies on predefined control signals, electrical conditions, and protocol rules rather than in-band reset for establishing the link and enumerating devices on the bus.

If you need to do a Warm Reset to allow the link to train to Gen speed. Your design, including the Hard IP for PCI Express and Configuration Bypass, can then run at Gen desired speed. Or maybe system reboot.

Let me know if anything still not clear, or I missinterpret your question.

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[sambkr]

Hi Wincent, 

let me summarize what I've understood.

It's possible for the Pcie Hard Ip working without shared perstn pin. Working with Cyclone 10 GX with AVMM design.

Perstn pin is used for "hot reset".

I will connect this pin to nconfig of FPGA. 

If the PC reset, how can I get the information of "broken link" and how the endpoint will ask for "hot reset" or "warm reset" or any reset to restart LTSSM for new link training. 

is this information into pcie data link layer ? TLP ? 

Do I have to create custom logic to drive perstn signal ? 

BR.

[wchiah]

Hi,

Based on my understanding While the PERST# (reset) signal is an integral part of the PCIe specification and is commonly used to reset and initialize PCIe devices, it is not strictly required for all implementations.

There are certain scenarios where a PCIe hard IP can work without the PERST# signal. For example, if the system ensures that the PCIe device is properly initialized through alternative means, such as software or other hardware mechanisms, the PERST# signal may not be necessary.

For information about reset and link training status you may refer to

https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/reset-status-and-link-training-signals-reset.html

I believe the explanation is better there.

Let me know if further clarification is needed.

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

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Regards,

Wincent_Intel