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In our setup (avery bfm with other qsys design (includes hard ips) for the very first pcie config read no response from pcie_ptile hard IP.
How can we identify whether ptile is timed out or not.
If the (config transaction) bus number is not matching with ptile bus number, ptile will simply timed out or it will send any response. Below is the message fetched: For reference please go through the tracker file.
==> @197352.642ns CFGRD0#10770 (bdf_1_0_0, offset 0)(req_id 0000, tag 000) (APCI_TRANS_cfg#1076f)
| fmt | typ |t| tc |t|a|l|t|t|e|att| at| length |
| 000b| 00100b |0|_ 0 _|0|0|0|0|0|0| 0 | 0 |_______ 001h ______|
|________ req_id: 0000 _________|___ tag: 00 ___|lbe: 0 |fbe: f |
| bdf.bus |bdf.dev|bdf.func|rsvd20|reg_no.ext|reg_no.low|rsv|
|______ 01 ___|__ 00 _|___ 0 __|_ 0 __|___ 0 ____|___ 00 ___| 0 |
04000001 0000000f 01000000
((Probe func_1_0_0))
quartus version:19.4
device used: 1SD280PT2F55E2VGS1
vcs version: 2019.06-SP2
Please let us know if any other information is required. If necessary we can provide the environment for debugging.
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Hi,
Is this problem happen during enumeration? Are you using the example design in Appendix D (page 211)?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf
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