FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6424 Discussions



I have a customer using the EMIF IP to create a DDR3 interface in a Stratix 10 and came across this parameter that is created in the 20.1 version of Platform Designer.j  The problem my customer had was this:

Using the A10 PCIe card from BittWare  (385A) and wrestling with parameter settings for DDR3 memory.. I’ve been building in Quartus 20 and generating EMIF IP based on settings BittWare published in their user guide.  I was able to get something working well, except for a few cards that misbehave with ECC errors when the FPGA die temperature goes above 85 deg C.

Looking at this again. BittWare provided me the EMIF IP file they use.  It was produced in Quartus 15 so I allowed Quartus 20 to upgrade the IP. All of the parameters reported by Platform Designer match the EMIF parameters I’ve been using... but the new EMIF works at higher temperatures (90+ deg C) !!

I performed a diff of the RTL produced by Platform Designer and discovered one parameter was different.

.PHY_DLL_CORE_UPDN_EN                       (1),

The EMIF with this set to ‘1’ operates at higher temps. I can’t find any description of this parameter or locate a switch in Platform Designer that might influence this setting.

What does this parameter do and how is it set?


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