PLL unlocked issue when use clock recovery module in Intel DisplayPort Rx IP

[watari]

Title:

PLL unlocked issue when use clock recovery module in Intel DisplayPort Rx IP

Hi forum members,

We encounter weird behavior when bitec_clkrec module which is a part of DisplayPort Rx IP is to regenerate recover clock via fractional PLL and PLL reconfiguration module around 93.2MHz.

Also, I already post this issue as below.

"DisplayPort Rx IP can't generate stable recover clock in clock recover module."

https://forums.intel.com/s/question/0D50P00004E8HoRSAV/displayport-rx-ip-cant-generate-stable-recover-clock-in-clock-recover-module

We suspect that PLL parameters is not suitable. Ex. VCO range, bandwidth setting, charge pump setting and so on.

Especially, we suspect a negative-feedback circuit of PLL is an instability by ex. causing wrong loop filter setting.

[Question]

Q1) Does ArriaV GX have like "Phase Frequency Detector" in "Altera fPLL" module ?

   I guess that this answer is yes. But we'd like to confirm it.

Q2) If we set bandwidth parameter as auto, do a fractional PLL with PLL reconfiguration logic automatically change suitable band width setting ?

Q3) How do we consider parameters of loop filter without EXCEL file ? Unfortunately, this IP is protected and automatically update PLL parameters by it self via PLL reconfiguration module.

Q4) Also, how do we consider and/or improve a transient response characteristic ? Because this IP (clkrec module) frequently change PLL parameter to follow a gap between write pointer and read pointer on FIFO by some parameters.

[Note]

This issue occurs our custom board and ArriaV evaluation board too.

Also, it occurs example design too.

Best regards,

[SreekumarR_G_Intel]

Hello Koji , Let me answer your question first , Q1: Yes , Intel PLL IP do have the PFD, Can you please refer below link Figure 1 PLL Architecture. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf. Q2:If the Bandwdith Preset values set as Auto means IP core choose the best possible bandwidth values to achieve the desired PLL settings. It might be outside the low and high preset range. Q3: Unfortunately no, Internal architecture of loop filter and its math is proprietary to Intel.I would recommend to use Calculator (excel sheet format) provided by Intel. Q4: I am not sure which module transient response you are talking about , Is that for PLL ? Can you kindly Clarify ? Note I am not aware of bitec IP. PLL can loss the lock in many ways , i am unsure about your setting can you let me know which example design you are talking about ? I am trying to think like.. Is it possible to realize your problem through simulation . can you please let me know how i can help you further ? Thank you , regards. Sree

[watari]

Hi Sree

Thank you for your reply.

I mention to you.

> Q2:If the Bandwdith Preset values set as Auto means IP core choose the best possible bandwidth values to achieve the desired PLL settings. It might be outside the low and high preset range.

Does parameter value of Bandwidth as Auto depend on an initial setting of desired output frequency on GUI of IP catalog of Quatrus even if we use Fractional PLL with PLL reconfiguration logic ?

> Q3: Unfortunately no, Internal architecture of loop filter and its math is proprietary to Intel.I would recommend to use Calculator (excel sheet format) provided by Intel.

Can we estimate these parameters with excel file even if the design use fractional PLL with PLL reconfiguration ?

Unfortunately,

> Q4: I am not sure which module transient response you are talking about , Is that for PLL ? Can you kindly Clarify ? Note I am not aware of bitec IP.

It is for PLL. But many parameters (maybe M value, some C counter value and so on) are calculated by bitec IP.

However, we can observe these parameters (*1) by Signal Tap between calculation logic and Altera PLL reconfiguration logic.

> can you let me know which example design you are talking about ?

> I am trying to think like.. Is it possible to realize your problem through simulation .

I use an example design of Intel DP IP (v17.1) as below on ArriaV Development Kit and HSMC DisplayPort 1.2 Daughter Card.

## IP directory

```

$QUARTUS_ROOT/ip/altera/altera_dp/

```

## ex. Simulation Model

```

$QUARTUS_ROOT/ip/altera/altera_dp/sim_example/av

```

## HMC DisplayPort 1.2 Daughter Card

https://bitec-dsp.com/product/hsmc-displayport-daughter-card/

We'd like to share a part of these parameters which are generated by bitec IP around lock lost timing.

But we can not share them on community forum...

Would you tell me your upload web site or something ?

*)

We can observe them as dprio_writedata (16bit bus), not mgmt_writedata (32bit bus).

[Additional Information]

We suspect bitec clkrec might ignore an inhibited clock frequency range which is defined by pdf and excel file.

Because failed clock frequency range involves this inhibited clock frequency range.

Best regards,

[SreekumarR_G_Intel]

Hello , I am sorry ..got into another stuff..:( Q2 : For the FPLL, Only "LOW" bandwidth setting allowed. Q3: Yes , Calculator is meant to achieve the frequency by varying M/N/Loop filter R and Charge pump current. There is option for private chat in the fourm. Can you please check ? Without interfacing with bitech IP i am not sure how to replicate your scenario ? Thank you , Regards, Sree