Hello All,I am developing a high speed digital video transfer interface between a video DSP and central memory of a PC for a frame grabber card. I use Altera Cyclone IV GX 22 chip with Altera PCIe hard IP core and Altera SGDMA core configured as Avalon ST (the video source - a self-made module) -> Avalon MM (the PCIe 4x core) transfer device in 64 bit mode, burst is enabled. The HW does not know where a frame ends because it is read back from a memory as simple data. The amount of bytes is specified in the descriptor list of the SGDMA by the SW. Unfortunately the SGDMA seems to have internal FIFOs and always ask for new data until they are full, even the SW did not ask for anything. This casues a pixel shift in the next frame when the needless data is sent into the central memory. The number of shifted pixels is clearly related to the width of the SGDMA burstcount signal (between SGDMA and PCIe). We tried to reset the core by SW at the beginning of every frame transfer but did not work. We tried to throw away the first dummy pixels but found the number of pixels is not fully stable but is changing. Has anyone experienced similar effects? The datasheet does not mention anything. Therefore no solution can be found in it. Regards, Istvan
The ST sink 'ready' signal is most likely tied to the FIFO not empty signal inside it so there wouldn't be an easy way to work around it in the IP. So basically when the SGDMA is idle you want the sink port to become blocking correct? If so you might find it easier to hack the modular SGDMA up on the altera wiki to do that. I think it would be just a matter of masking the sink 'ready' signal with (length != 0).
I am not familiar with this core. Is it available for commercial use? Where can I get more information about it? Is it available from Altera website directly?
it's on www.alterawiki.com Do a search for "modular" and you will find it. You can use it for commercial use and modify it if necessary. The documentation can be found in each of the cores under the /ip directory.