FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

Precise sampling rate and decimation

Altera_Forum
Honored Contributor I
1,124 Views

Hi there, I have spent some time making a MAC based digital 1000 tap filter on a DE1 board. The ADC rate into the filter module is 40khz... However i would like to down sample my data. I am aware of the rudiments of polyphase decimation and that it's strength is; that less computation is used in comparison to simply tossing samples out. But what i really would like to to to call a precise integer value sampling rate. So, if a person wants for example 23Khz sampling rate they can have that. Perhaps I am naive to this but, is the only way to do this to interpolate to increase samples then reduce samples with decimation? If so is this common practice, or is it more common to produce standard sampling rates like, 40k, 20k, 13.3k, 10k, 8k, 6.6K etc..? I would greatly appreciate any creative speculation or any veteran advice:D. 

 

Best Regards  

H
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
73 Views

What you want to do is possible but I don't know the details of how to implement it. I've used audio sample rate converter ICs like this in the past: 

 

http://www.analog.com/en/products/audio-video/sample-rate-converters/ad1893.html#product-overview 

 

The chip figures out the input to output sample rate ratio from the input and output sample rate clocks and it does this continuously on the fly. This particular chip is limited to input : output sample rate ratios between 1:2 and 2:1. This would be a fun project to figure out. Good luck with it.
Altera_Forum
Honored Contributor I
73 Views

Thanks rsefton, Ill check it out;)

Altera_Forum
Honored Contributor I
73 Views

 

--- Quote Start ---  

Thanks rsefton, Ill check it out;) 

--- Quote End ---  

 

 

you can design "variable rate converter" or call it variable decimator in the FPGA. It is a bit of learning curve. It requires plenty memory for coefficients but only uses few of them at a time.
Reply