I am trying to use the FIR compiler and a DE2 board to create a 1 kHz audio fitler. I have verified the input signal is my desired signal sampled at 48 kHz and I have used the following configuration:ast_sink_error: (00) ast_sink_valid: 1 ast_source_ready: 1 clk: 48 kHz clk signal ast_sink_data: input signal When I compile the code and program the FPGA the input signal seems to be passed on without any filtering taking place. Has anyone encountered this before? Thanks in advance!
There is a very simple test to check that your filter implementation is same as designed response.insert an impulse input and you should see your output equals coefficients though scaled in some way. an impulse input is all zeros except for one sample having a value high enough for your representation e.g. 1023 then zeros for 11 bit signed. since it is real time you will need to repeat this input from time to time and capture output