Problem about FFT core

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Hi,everybody. 

RecentlyI have used the FFT core 8.0 and occured some problems.  In the dsp builer,I simulate the FFT and cascaded the IFFT module.The input signal is sine wave.The result is just right,output of real is sine wave.And then,I do this processing in the Quartus II:  Firstly,I set a ad-da sampling module for sampling signal from the outside of the borad.When the signal comes out of ad-sampling module,I directly send the signal to FFT and IFFT module,and in the end the result is abnormity(frequency is as same as the input ,but wave form is abnormal having some glitches).  So I try to find the problem,I guess the signal can't directly send to the FFT core,may be processed as a frame form(256 points,FFT points is 256,streaming).I add a fifo as a buffer but it doesn't work.I don't know how to set the signal as a 256 point frame.  Any help will be appreciated.  ps: FFT control module.I try to frame the input signal in this module,it doesn't work. module input_ctrl(clk,reset_n,sink_ready,ad_in,sink_sop,sink_eop,sink_valid,real_in,imag_in,sink_error); input clk; input reset_n; input sink_ready; //input full; input [15:0] ad_in; output sink_sop; output sink_eop; output sink_valid; output [15:0] real_in; output [15:0] imag_in; output [1:0] sink_error;   reg [7:0] count; reg sink_sop_r; reg sink_eop_r; reg [15:0] in_mem [255:0]; reg [15:0]real_in; assign sink_error=2'b00; assign sink_valid=sink_ready; assign imag_in=16'b0000000000000000;  always @(posedge clk)  begin    if(reset_n==0)  count<=0;  else   begin  if (sink_ready == 1)    if (count == 0)  begin  sink_sop_r <= 1'b1;   sink_eop_r <= 1'b0; // assert sop  //sink_valid <=1'b1;  count <= count + 1;  in_mem[count]<=ad_in;  real_in<=in_mem[count];  end    else if (count == 255)  begin  sink_eop_r <= 1'b1;  in_mem[count]<=ad_in;   real_in<=in_mem[count];   count <= 0;  end    else  begin  in_mem[count]<=ad_in;  real_in<=in_mem[count];  count <= count+1;  sink_sop_r <=0;  sink_eop_r <=0;  end     end  end assign sink_sop =sink_sop_r; assign sink_eop =sink_eop_r;  endmodule