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Altera_Forum
Honored Contributor I
1,362 Views

Problem simulating Altera 10GbE MAC

Hello! 

 

I am working on an existing project, updating the design's MAC core from Altera's tse to the 10GbE. 

I want to verify that the changes I've made to implement the new MAC core is working by simulating packets through the design by means of a loopback. 

However, I am having problems adding some of Altera's submodules generated with QSYS to the modelsim project. 

I believe it's because the particular submodules are protected (encrypted). 

When I run the do script in ModelSim I get eight of the following error messages: ** Error: nofile(37): in protected region 

during design optimization. 

I've also noticed the submodules in question are not being added to the appropriate modelsim library like all the other submodules. 

 

Is there some trick to simulating an IP core? I must be doing something wrong. 

 

I'm using Quartus 13.0 64-bit Full Edition and ModelSim SE 10.0. 

 

Sorry if my question isn't composed very well. I'm still very new to this FPGA stuff. 

 

Thanks for any help!
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3 Replies
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

Hello! 

 

I am working on an existing project, updating the design's MAC core from Altera's tse to the 10GbE. 

I want to verify that the changes I've made to implement the new MAC core is working by simulating packets through the design by means of a loopback. 

However, I am having problems adding some of Altera's submodules generated with QSYS to the modelsim project. 

I believe it's because the particular submodules are protected (encrypted). 

When I run the do script in ModelSim I get eight of the following error messages: ** Error: nofile(37): in protected region 

during design optimization. 

I've also noticed the submodules in question are not being added to the appropriate modelsim library like all the other submodules. 

 

Is there some trick to simulating an IP core? I must be doing something wrong. 

 

I'm using Quartus 13.0 64-bit Full Edition and ModelSim SE 10.0. 

 

Sorry if my question isn't composed very well. I'm still very new to this FPGA stuff. 

 

Thanks for any help! 

--- Quote End ---  

 

 

The solution: After you get this no file/error in protected context in ModelSim's transcript window, go to Modelsim's main window under Tools/Tcl/Execute Macro search for the folder named <component_name>_sim/mentor and select and run the file msim_setup.tcl. Where I have assumed your instance of the megacore is <component_name>. Then, run a .do file from the modelsim transcript which only compiles your design files (not the libraries or megafunction related files) from modelsim's transcript window. You can cut and paste it into the transcript from the bottom half of the .do which created the error in the first place including the vsim, wave and run -all lines. 

 

Apparently, there are things in the .tcl which must be used to setup modelsim before it can load all files for a certain megacores, including certain high speed phy cores like XAUI. Actually, this is vaguely inferred from table 1-5 of Altera's "Simulating Altera Designs": in www dot altera dot com/literature/hb/qts/qts_qii53025.pdf. Unfortunately, Altera did not post it as a work-around on page 15 of www dot altera dot com/literature/rn/archives/rn_qts_110sp1.pdf, where they list this as an issue for low latency phy megafunctions with 10 Gps data paths. I had this same error for a XAUI PHY. My guess is that Altera builds their interoperability fixes with various simulation tools into their .tcl setup files for those tools. It is wise to try to use them to try and resolve these issues.
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

The solution: After you get this no file/error in protected context in ModelSim's transcript window, go to Modelsim's main window under Tools/Tcl/Execute Macro search for the folder named <component_name>_sim/mentor and select and run the file msim_setup.tcl. Where I have assumed your instance of the megacore is <component_name>. Then, run a .do file from the modelsim transcript which only compiles your design files (not the libraries or megafunction related files) from modelsim's transcript window. You can cut and paste it into the transcript from the bottom half of the .do which created the error in the first place including the vsim, wave and run -all lines. 

 

Apparently, there are things in the .tcl which must be used to setup modelsim before it can load all files for a certain megacores, including certain high speed phy cores like XAUI. Actually, this is vaguely inferred from table 1-5 of Altera's "Simulating Altera Designs": in www dot altera dot com/literature/hb/qts/qts_qii53025.pdf. Unfortunately, Altera did not post it as a work-around on page 15 of www dot altera dot com/literature/rn/archives/rn_qts_110sp1.pdf, where they list this as an issue for low latency phy megafunctions with 10 Gps data paths. I had this same error for a XAUI PHY. My guess is that Altera builds their interoperability fixes with various simulation tools into their .tcl setup files for those tools. It is wise to try to use them to try and resolve these issues. 

--- Quote End ---  

 

 

Thanks for the help! 

I wound up doing something similar and it appears to work so far.
Altera_Forum
Honored Contributor I
51 Views

I was getting having problems simulating a XAUIcore with multiple errors like# ** Error: nofile(38): in protected region 

(when vopt was enabled) or# ** Fatal: Error occurred in protected context.# Time: 0 ps Iteration: 0 Protected: /test_bench/UUT/XAUI_IF/xaui_phy_inst/genblk2/alt_xaui_phy/genblk2/sxaui_0/imp_soft_pcs/alt_soft_xaui_pcs/xaui_rx/imp_soft_pcs/pcs_deskew/imp_soft_pcs/deskew_chan3/imp_soft_pcs/deskew_ram File: nofile# FATAL ERROR while loading design# Error loading design# Error: Error loading design 

I solved this error problem by editing the <design_instance>_sim/mentor/mssim_setup.tcl file, which is generated by the Megawizard (and Qsys?). I added my own libraries using their ensure_lib/vmap syntax. I also added my own alias followed by the vcom or vlog lines, using their syntax, for my design files under theirs in the 'Compile the design files in the correct order section'. The alias allows you to type single word in modelsim's transcript window to perform a multitude of actions. Following their paradigm, I added my own alias for elaborating my design under their Elaboration section. To make sure that I did not miss any library files, I copied their vsim line into my elaboration alias definition, I added my own desing libraries to that file and then replaced their $TOP_LEVEL_NAME, with my test bench entity name. 

 

I also ld_mydesign as an alias under the# Compile all the design files and elaborate the top level design 

section. When I defined this last alias, I couldn't resist add to that alias definition the lines: 

add wave * 

view structure 

view signals 

run -all  

Finally, just for reminder's sake, I added my alias definitions under the# Print out user alias section. 

These are printed out when modelsim executes the .tcl file. I then saved this tcl file as <my_tcl_file_name>.tcl in the directory <Project_folder>/simulation/modelsim, which is where ModelSim finds its modelsim.ini file. 

 

This .tcl file can now be read in by modelsim either through the Tools/Tcl menu or by typing  

do <my_tcl_file_name>.tcl 

in ModelSim's transcript window. After 'do <my_tcl_file_name>.tcl' in ModelSim's transcript window, I simply type 

ld_mydesign 

in the transcript window. No more of those nasty loading errors!
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