FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

Problem with FIR COMPILER 9.1

Altera_Forum
Honored Contributor II
1,001 Views

Hi everybody, 

 

I'm working with a Cyclone 3 EP3C120 Dev. Board and I have some problems with the FIR Compiler 9.1 (also with 9.0). 

 

I got eight sets (four Lowpass and four Bandpass), everyone with 159 Coeffs. When I do the simulation it looks fine but after implementing the software on FPGA the scope shows me something strange. It seems that the scale doesn't fit anymore. The input signal has a VPP around 150mV and right after the filter VPP is about 2.5V. Right behind the filter I scaled the signal to 14 bit because of the max width of the D/A converter. The filtered signal looks like if its jumping from + to - again and again. 

 

Can anyone help?  

 

T-4444
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
270 Views

How did you scale the signal to 14 bits?

0 Kudos
Altera_Forum
Honored Contributor II
270 Views

Hi, 

 

I scaled it by using a ROUND block. Settings as follow: 

 

BUS TYPE: signed Integer 

[Numer of Bits].[] : 44 

Number of LSB Bits to remove: 30 

Rounding Mode: Truncate 

 

The output bitwidth from the fir filter is 50 bits. 

 

thx for your reply! 

 

T-4444
0 Kudos
Altera_Forum
Honored Contributor II
270 Views

I don't understand. You say that the output of the filter is 50 bits wide, but the input of your round block is 44 bits? How do you connect them together? And do you really need that many bits? 

Does your D/A converter accept signed or unsigned input? If it's unsigned it could explain your problem.
0 Kudos
Altera_Forum
Honored Contributor II
270 Views

Thanks for the hint about D/A converter (signed or unsigned), I'm still compiling the projekt (takes about 2h). I updated my design including an offset so, that there is no negative signal anymore.  

 

I connected the FIR block directly with the ROUND block an there is no error even if the witdhs don't match. I've done this to reduce the range of the signal. 

 

And I need the 50 Bits to reach the required 70db fall (concerning one of my bandpass filters). 

 

I let you know if the new design works better. 

 

T-4444
0 Kudos
Altera_Forum
Honored Contributor II
270 Views

It is important to know how the two vectors are connected... If they are aligned on the MSB (i.e. the low 6 bits are ignored) then it is ok. But if they are aligned on the LSB and the 6 most significant bits are disconnected, then you'll get a very weird output.

0 Kudos
Altera_Forum
Honored Contributor II
270 Views

I truncated the last bits (LSB cut off), so the original signal is still present but in reduced range.

0 Kudos
Altera_Forum
Honored Contributor II
270 Views

Thanks to Daixiwen, the problem was my D/A converter which doesn't accept signed signals as input. 

 

T-4444
0 Kudos
Reply