There is a "Frequecy_Counter" IP in SOPC and Qsys, but there don't seem to be any instructions on how to use it. When I click on the "Datasheet" link for the IP, it brings me to the "ub_embedded_ip.pdf" which does not include any instructions for this device. System.h lists that it is there when I include it in my NIOS processor, but there are no support functions included in the BSP to give me a clue on how to use it. Altera and Off-site searches would lead me to believe that nobody on the planet has ever used this IP. Can that be true?Does anybody know where there are instructions on this IP, or have any ideas about register descriptions and which of the 3 clocks are which?
Follow up:This appears to be just another half-baked marketing ploy by Altera. Even after you reverse-engineer their bloated device, you find that it is embarrassingly easy to lock-up. Just have one of the two input frequencies equal to zero and it enters a state where only a power-down will reset it (To understand why there needs to be 2 input frequencies, just consult the instructions. Ha!). Useless! But they get to put it in the list of "Features", just don't try to find the instructions on how to use it, or expect it to work with a very common input state without locking up. So the reason that "...nobody on the planet has ever used this IP" is because it performs so poorly that it is better to just write your own. That's a couple of days of my time that I'll never get back. Maybe someday I'll learn better.
donq -Where did you find this thing? I don't see it anywhere in Qsys and searching by Google or on the Altera site comes up empty. Did you pull it out of a reference design or something? Not an "official" Altera core as far as I can tell.
Found it at Qsys : Library : Peripherals : Debug and Performance : Frequency_counter"The main source file starts with this:
// (C) 2001-2014 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. //Frequency checker //Author: Harold Wang `timescale 1ns/1ns module frequency_counter# ( parameter CROSS_CLK_SYNC_DEPTH = 2, parameter REG_WIDTH = 32, parameter DEFAULT_MAX_CNT = 1000 ) ( input reset, input avs_clk, input avs_address, input avs_write, input avs_read, input avs_byteenable, input avs_writedata, output reg avs_readdata, input ref_clk, input des_clk ); //Local parametersetc. If it's in the menu, and the code has the Altera copyright, then it sure wasn't written by me! And, no, I didn't find it on Google or on the Altera site either. That's sort of the point. It is in the main IP library (at least on my machine, and i did not put it there, and I'm the only user), but there is zero info anywhere about using it. Looks good on paper, but reality is a completely different issue.
Doesn't exist in Quartus Prime, and no mention in the revision history of the Embedded Peripherals User Guide. But I also have Quartus II 13.0 installed and it was in the Qsys library exactly where you said it would be.I get that IP cores come and go, but there should at least be a record somewhere and access to older versions of the documentation in case you're using older tools as you are. There is absolutely no mention of that core anywhere on the Altera web site that I can find, which is pretty incredible really. Nothing in the knowledge base, nothing on this forum. Like it never existed. I would open a SR with Altera just to get an old copy of the Embedded Peripherals User Guide, and to find out in what versions of Quartus it existed. Altera's documentation management is pitiful. If you're running Quartus v13.0 (or any other version) and instantiate a component in Qsys, the documentation link should take you to v13.0 of the document, not v16.0 where the component no longer exists.
FYI: I'm only using 13.1 because they *DROPPED SUPPORT* for Stratix III an all subsequent versions. The Stratix III was once their "Flagship" product! And now they don't support it! In fact, even in V13, *many* of the tools specifically don't work for Stratix III. That's some of the reason I start off with a somewhat bad attitude about Altera and Quartus in particular. They've never supported prior versions of Quartus once they move on, and current versions of Quartus do not support the FPGA that we have many, MANY thousands of dollars invested into. Grrrr...I also maintained copies of some previous versions of Quartus documentation, and I was unable to find any reference to "frequency_counter" there either. It seems to be a complete orphan. The real problem is that even after I reverse engineer the IP, I find that it is ridiculously easy to put it into a state where there is no recovery except for power-down / power-up. Why would they ever put such a completely untested item in their library? And it caused me to question whether I should be using any of their other IP, whether it has instructions or not. Things like this give me the impression that Altera really just doesn't care.
--- Quote Start --- There is a "Frequecy_Counter" IP in SOPC and Qsys, but there don't seem to be any instructions on how to use it. --- Quote End --- That IP has "set_module_property INTERNAL true" in it's _hw.tcl which means that it is not intended to be used by customers and should not be visible under normal installations. Use it at your own risk?
--- Quote Start --- That IP has "set_module_property INTERNAL true" in it's _hw.tcl which means that it is not intended to be used by customers and should not be visible under normal installations. --- Quote End --- Not in my totally default installation (and not in at least one other users installation.) Maybe they changed it sometime after they also stopped supporting my Stratix III.
# +----------------------------------- # | module altera_avalon_data_pattern_checker # | set_module_property DESCRIPTION "Frequency Counter" set_module_property NAME frequency_counter set_module_property VERSION 13.1 set_module_property INTERNAL false <-----------------************* set_module_property GROUP "Peripherals/Debug and Performance" set_module_property AUTHOR "Altera Corporation" set_module_property DISPLAY_NAME "Frequency Counter" set_module_property DATASHEET_URL http://www.altera.com/literature/ug/ug_embedded_ip.pdf set_module_property TOP_LEVEL_HDL_FILE frequency_counter.v set_module_property TOP_LEVEL_HDL_MODULE frequency_counter set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE false set_module_property ELABORATION_CALLBACK elaborate # | # +-----------------------------------
Roberto,Thanks. I've got something that works now and have 12 of them installed in my NIOS processor. It just seemed like a no-brainer to use a built-in Altera supplied core for installation in an Altera system. Little did I know the disaster that would turn into.