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Altera_Forum
Honored Contributor I
1,220 Views

FIFO IP is getting empty at a faster rate

Hi, 

 

I'm using a FIFO IP with width of the fifo being 16 bit and the depth of the fifo buffer is 16384 words. I'm using the MAX10 development kit and interfacing it with Matlab. The baud rate is set to 115200 bps. Data is being written in the fifo buffer continuously and when I send read command from matlab, data is being read from the fifo buffer. It happens sometimes that the fifo buffer is getting emptied at a faster rate than data being written into it and my matlab program terminates. Can anyone please help me with this issue. 

 

Thanks
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8 Replies
Altera_Forum
Honored Contributor I
12 Views

Did you use an UART Core inside MAX10 to receive or send data from/to Rx/Tx pins ? Did you set the baud rate of UART core to 115200 bps?? have you taken care of FIFO overflow?

Altera_Forum
Honored Contributor I
12 Views

Hi,  

 

Thanks for your reply,  

I did use the UART core and set the baud rate to 115200 bps and also have taken care of FIFO overflow and underflow. Whenever the fifo gets empty, it'll automatically gets filled up, the code works this way.  

 

Thanks,
Altera_Forum
Honored Contributor I
12 Views

Make sure you have a proper level shifting buffer between FPGA I/O pins & the external RS-232 connector since the I/O buffers on most Altera FPGA families do not comply with RS-232 voltage levels, and may be damaged if driven directly by signals from an RS-232 connector.  

 

 

--- Quote Start ---  

It happens sometimes that the fifo buffer is getting emptied at a faster rate than data being written into it and my matlab program terminates. Can anyone please help me with this issue. 

--- Quote End ---  

 

 

Can you elaborate more on the problem? How fast it is getting emptied?
Altera_Forum
Honored Contributor I
12 Views

You never indicate the rate that data is being written to the FIFO.

Altera_Forum
Honored Contributor I
12 Views

 

--- Quote Start ---  

You never indicate the rate that data is being written to the FIFO. 

--- Quote End ---  

 

 

Hi, 

 

The clock connected to the fifo IP core is 50 MHz, and my data is 16 bit and the depth of the buffer is 16384. So if I do the calculation then a data is being written into the buffer in 2x10^-8 sec, so the total time to fill up the buffer is ( (1/50MHz) * 16 * 16384 = 0.005 sec ). The baud rate is set at 115200 bps so the fifo is getting completely filled up at a faster rate than it's being read out. In this case I will always have some data left in the fifo. I think I messed up the calculation( by not taking into consideration the write request ). Please kindly correct me if I'm wrong.  

 

Thanks,
Altera_Forum
Honored Contributor I
12 Views

 

--- Quote Start ---  

Make sure you have a proper level shifting buffer between FPGA I/O pins & the external RS-232 connector since the I/O buffers on most Altera FPGA families do not comply with RS-232 voltage levels, and may be damaged if driven directly by signals from an RS-232 connector.  

 

 

 

Can you elaborate more on the problem? How fast it is getting emptied? 

--- Quote End ---  

 

 

Hi, 

 

Thanks for this information. I didn't know that. I need to look into this too.
Altera_Forum
Honored Contributor I
12 Views

swarnava9 - 

 

Do you know how to use SignalTap? SignalTap will show you very quickly what's happening. I'm assuming here that SignalTap works in MAX10 devices (I've never used MAX10).
Altera_Forum
Honored Contributor I
12 Views

Hi All, 

 

Thanks for your advice. It worked. There was a bug in my code. Thanks again to all for your time. 

 

Thanks,