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Valued Contributor III
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Question about simulation of VIP cores

Hi, 

I'm doing a simulation of Clocked Video Input with Altera-Modelsim using NativeLink, but it seems the IP cores doesn't respond to my testbench as the attachment below, while I have successfully simulated the reconfiguration of altera's pll. 

 

My question is that if the VIP cores support simulation or not, are there any differences between simulation of CVI and PLL? 

Thanks for reply!
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Highlighted
Valued Contributor III
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--- Quote Start ---  

Hi, 

I'm doing a simulation of Clocked Video Input with Altera-Modelsim using NativeLink, but it seems the IP cores doesn't respond to my testbench as the attachment below, while I have successfully simulated the reconfiguration of altera's pll. 

 

My question is that if the VIP cores support simulation or not, are there any differences between simulation of CVI and PLL? 

Thanks for reply! 

--- Quote End ---  

 

 

Hi, 

 

how does your testbench lookslike ? 

 

Kind regards 

 

GPK
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Highlighted
Valued Contributor III
5 Views

 

--- Quote Start ---  

Hi, 

 

how does your testbench lookslike ? 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

Hi, GPK 

I have attached my testbench, thanks for help!
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Highlighted
Valued Contributor III
5 Views

 

--- Quote Start ---  

Hi, GPK 

I have attached my testbench, thanks for help! 

--- Quote End ---  

 

 

Hi, 

 

are you using a synchronous reset ? It looks to me that in your testbench the clocks starts after releasing the reset.  

 

Kind regards 

 

GPK
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Highlighted
Valued Contributor III
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--- Quote Start ---  

Hi, 

 

are you using a synchronous reset ? It looks to me that in your testbench the clocks starts after releasing the reset.  

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

Hi, GPK 

As quoted from the VIP user guide, "The MegaCore function is asynchronously reset when rst is asserted high. The reset must be de-asserted synchronously with respect to the rising edge of the is_clk signal." 

 

And I have commented the delay for the clocks initial as below, but it still doesn't work. 

Thanks again! 

 

initial  

begin  

dclk_in = 0; 

//#120; 

forever# 25 dclk_in = ~dclk_in;  

end  

 

initial 

begin 

sys_clk = 0; 

//#120; 

forever# 5 sys_clk = ~sys_clk; 

end
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Highlighted
Valued Contributor III
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--- Quote Start ---  

Hi, GPK 

As quoted from the VIP user guide, "The MegaCore function is asynchronously reset when rst is asserted high. The reset must be de-asserted synchronously with respect to the rising edge of the is_clk signal." 

 

And I have commented the delay for the clocks initial as below, but it still doesn't work. 

Thanks again! 

 

initial  

begin  

dclk_in = 0; 

//#120; 

forever# 25 dclk_in = ~dclk_in;  

end  

 

initial 

begin 

sys_clk = 0; 

//#120; 

forever# 5 sys_clk = ~sys_clk; 

end 

--- Quote End ---  

 

 

Hi, 

 

to be honest I was not convinced that the reset is the root cause, but you never know .... 

In my experience HiZ often means that nothing is connected to the outputs. Do run a complete Quartus P&R. If yes did you some strange messages that something is missing ??? Or have your core tri-state capable outputs ? 

 

Kind regards 

 

GPK
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Highlighted
Valued Contributor III
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--- Quote Start ---  

Hi, 

 

to be honest I was not convinced that the reset is the root cause, but you never know .... 

In my experience HiZ often means that nothing is connected to the outputs. Do run a complete Quartus P&R. If yes did you some strange messages that something is missing ??? Or have your core tri-state capable outputs ? 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

Hi, GPK 

Yes, I did P&R, but no strange messages turned out. Do you have any other suggestions? 

Thanks again.
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Highlighted
Valued Contributor III
5 Views

 

--- Quote Start ---  

Hi, GPK 

Yes, I did P&R, but no strange messages turned out. Do you have any other suggestions? 

Thanks again. 

--- Quote End ---  

 

 

Hi, 

 

is it possible for you to look deeper into the IP block, in order to find out whether there are parts of the block running ? 

 

BTW: I found this remark in the documentation 

 

RTL Simulation Reports Errors When Using Verilog HDL 

EDA RTL simulation started from the Quartus II software reports errors in the 

ModelSim® simulator for designs containing Video and Image Processing Suite 

MegaCore functions when the output files are in Verilog HDL. 

Affected Configurations 

This issue affects configurations that use NativeLink to run a ModelSim simulation 

from Verilog HDL. 

Design Impact 

An error message reports that software cannot find the Altera library. 

Workaround 

Compile the file db/alt_cusp90_package.vhd to the Altera library. To perform this 

compilation, modify the top-level .do script in the simulation/modelsim directory. 

Solution Status 

This issue will be fixed in a future version of the Video and Image Processing Suite. 

 

Kind regards 

 

GPK
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