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Altera_Forum
Honored Contributor I
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Question about streaming video protocol

Hi all. 

Well, I know that CVI converts a generic input into an avalon st protocol compatibile data signal. 

Now, in my sistem i get a 27MHz pixel clock, while my video system is clocked @50MHz, and I suppose Avalon Streaming peripherals are clocked in @50Mhz to. in vip ug they say that  

"Video data packets are used to transmit video data between the MegaCore functions. 

A video data packet contains the color plane values of the pixels for an entire progressive frame or an entire interlaced field." 

but if i have a 27MHz pixel clock as input(and a fifo of 720 pixel), how are the video color planes sent over the interface? as "bursts" of 720 pixel clocked @50MHz? 

data valid is high from the second pixel to the last one? 

 

I have this question becouse I have to count the values of each Y to perform an histogram of the lumas for a single frame, but I don't know wih clock should I use to increase a counter for each pixel. 

P.s. I am not using the architecture suggested in this thread http://www.alteraforum.com/forum/showthread.php?t=1861&highlight=histogram
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4 Replies
Altera_Forum
Honored Contributor I
54 Views

Hi Phate, 

 

The Video ST interface transfers data synchronously with the system clock (50MHz in your case) therefore all signals in the interface is synchronised to the 50MHz clock. The interface includes two flow control lines: Valid and Ready. The Valid line is used by a source to indicate when valid (new) data is available on the data lines. The Ready line is used by the sink to indicate when it is able to recieve new data. If Ready is high, the source will output data as it becomes available and will set the Valid line high for each data word it outputs. If it has no data to output, it will make the Valid line low.  

 

In your example, since new pixel data arrives at a rate of 27MHz (assuming you output the colour planes in sequence), and since your system clock is almost twice as fast, the Avalon ST output will set the Valid line low almost every second pixel being transferred. If you wanted to count the pixels in a line, it would look something like this (in VHDL) 

 

process (Clk, Reset) 

begin 

if Reset = '1' then 

Count <= 0; 

elsif Clk'event and Clk='1' then 

if ST_Valid = '1' then 

Count <= Count + 1; 

end if; 

end if; 

end process; 

 

Clk is the 50MHz clock and ST_Valid is the Valid line on the ST interface.  

 

The Valid signal is high for every new word being transferred - not only for pixel data. Remember that each packet starts with a header word and that each video frame / field is preceded by a control packet. You have to implement a state machine that keeps track of where you are in the transfer process. The state machine would then have an output like VideoActive which you set high for as long as there is actual pixel data coming in. This signal, together with the Valid signal is used to enable your counters. 

 

I hope this helps. Ask if it is not yet clear. 

Regards, 

Niki
Altera_Forum
Honored Contributor I
54 Views

hi Niki, thanks a lot for your reply. 

Yes, out from the CVI i have color planes in sequence. Then I add a color plane sequencer so in order to get two planes in parallel. 

I think I've understand. 

 

in sequence, only for video pakets, I have ...YcYcYcYcYcYc... but this is the flow for all the (720*240) pixels of my field, only when also datavalid is asserted. so I could count all pixels @50MHz clock. 

but what if they are transmit in parallel? 

I think they should be like this  

[15:8]YYYYYYYYYYYYY 

[7:0]ccccccccccccccc 

and they are transmitted only when datavalid is asserted(and i am in a video data paket sequence) .. they are still clocked @50MHz , isn't it?
Altera_Forum
Honored Contributor I
54 Views

Hi Phate, 

 

If the colour planes are sent in parallel then your data bus in your ST link becomes 16-bits instead of 8-bits wide, but the Valid, Read, SoP and EoP signals remain one bit wide and they apply to the full 16-bit word. So the Y and Cr/Cb values are transferred simultaneously. It is sill only a single ST link and not two separate ST links. Eveything is still clocked at 50MHz, but the Valid signal will be low more often since you transfer pixels now at about 13.5MHz instead of 27MHz. 

 

Regards, 

Niki
Altera_Forum
Honored Contributor I
54 Views

edit: writing new (correct) code.

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