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JJame30
Beginner
185 Views

SATA 2 in Quartus 14.0

Hi,

I am working on 2.5'' SATA II SSD (WR2SF256G-JFITI). using ALTGX ip for transceiver configuration. kindly share reference documents for configuration settings details for speed negotiation using ALTGX_RECONFIG.

Tool: Quartus 14.0

FPGA: STRATIX 4 (EP4SGX30NF45I3N)

 

 

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9 Replies
CheePin_C_Intel
Employee
65 Views

Hi,

 

As I understand it, you have some inquiries related using SIV device for SATA. To ensure we on are the same page, would you mind to further elaborate on "reference documents for configuration settings details for speed negotiation using ALTGX_RECONFIG"?

 

For example, what is the configuration settings details that you are referring here?

 

Just wonder if you have looking for some documentation which discuss about rate change for SATA application in SIV devices? If yes, you may try to refer to AN 625 - Implementing SATA and SAS Protocols in Altera Devices (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an635.pdf) to see if it is helpful to you.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

JJame30
Beginner
65 Views

Sir,

For SATA 2 effective data rate is 3000 Mbps. Then why speed negotiation is required? we can set data rate in ALTGX as 3000 Mbps directly. right?

CheePin_C_Intel
Employee
65 Views

Hi,

 

For your information, speed negotiation is required during initialization to help to establish a common speed between SATA devices. 

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

 

JJame30
Beginner
65 Views

Hi Sir,

In application note 625, it is mentioned that (Page no.12) :

*Connect the reconfig_data[15:0] port to the 16 least significant bit (LSB) of the

word from the new .mif.

*Connect the reconfig_address[5:0] port to the 6 most significant bit (MSB) of the

word from the new .mif.

 

i have data(16 bit) and address (6 bit) port in top level entity. how to map it to .mif file?

CheePin_C_Intel
Employee
65 Views

Hi,

 

For your information, regarding your previous note on the MIF info mapping, in the reduced MIF, the 6 MSBits of the MIF data = reconfig address while other LSBits = reconfig data. The MIF file is generally stored inside a ROM. You may then connect the 22 bits output of the ROM according to the port mapping mentioned to reconfig_address and reconfig_data at top level.

 

Thank you.

JJame30
Beginner
65 Views

Hi,

From AN-635-1.1, understood that there are 2 methods for interfacing SSD with Stratix IV by SATA Protocol.

 

  1. Re-configuring only the transmitter datapath data rate (Data rate division in TX).
    1. In this no .mif generation required. Right ?
    2. By this method, can we read back from SSD also ?
  2. Re-configuring the TX and RX CDR PLL across SATA data rates
    1. .mif genetation required. Right ?

 

 

 

 

CheePin_C_Intel
Employee
65 Views

Hi,

 

Please see my responses to your latest inquiries specific to the XCVR dynamic reconfiguration:

 

1. Re-configuring only the transmitter datapath data rate (Data rate division in TX). In this no .mif generation required. Right ?

[CP] Yes, you are right. YOu can perfor data rate division by controlling the rate_switch_ctrl[1:0].

 

2. Re-configuring the TX and RX CDR PLL across SATA data rates .mif genetation required. Right ?

[CP] Yes, you are right.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

JJame30
Beginner
65 Views

Sir,

I am attaching my SATA 2 project simulation images.

In host transmitted SOF , but not receiving properly in rx device.

similarly, transmitted SYNC after every 256 Data dword, it is also not receiving.

please help me in solving these issues.

 

IP used: ALTGX, ALTGX_RECONFIG, ATLPLL

Data width: 32 bit.

Interface frequency: 75 MHz

 

 

CheePin_C_Intel
Employee
65 Views

Hi,

 

Thanks for your update. Sorry as I am not very familiar with the SATA packets. However, based on the Modelsim simulation, it seems when the TX data pattern changes, the RX is capturing invalid or corrupted data. This seems strange as generally in the Modelsim simulation, we do not have SI issue.

 

To facilitate further debugging:

 

  1. Just wonder if you have had a chance to perform a loopback within the same duplex instance to see if similar issue occur? Just to further narrow down the issue.
  2. Would you mind to share with me a high level block diagram of you modules and interconnects for better understanding.
  3. Just wonder if you have had a chance to screenshot all the Native PHY status signals ie ready, reset, CDR lock, syncstatus just to ensure the XCVR is working fine.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

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