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Altera_Forum
Honored Contributor I
824 Views

SDI II Core, Reconfiguration does not work. Reconfig_busy stays low

Hi All,  

 

I'm implementing the SDI II cores in one of our new design which uses an ARRIA V and so far i'm unable to get the reconfiguration to work. 

 

What I have is:  

- ARRIA V starters kit  

- SDI HSMC board 

- Stratix V reference design for SDI II 

- ARRIA V Initial reference design for SDI II  

- read every little piece of info that is available on the SDI I & II cores. we've been using SDI I for many years. 

 

I'm able to get the reference design to work so that's good but it does not suit my needs and i'm unable to change it in the way i need.  

unfortunately i cannot signaltap in the signals of that design to figure out what goes wrong.  

 

What I did:  

- create a new project for Arria V starterskit 

- instantiated a triple rate SDI II Core, receiving side only from the megawizard. 

- instantiated a transceiver reconfiguration controller from the megawizard.  

- used the reconfiguration management code from the Arria V reference design.  

- connected all the signals in a .bdf file ( i like to work the schematic way).  

- created a signaltap file to monitor the reconfiguration management and SDI II Core 

 

As far as i am concerned this is everything i need to get a simple SDI triple rate receiver. Do you guys agree?  

 

What my observations are:  

 

- when I change video format the SDI II core requests a reconfiguration ( rx_sdi_start_reconfig goes high ) 

- reconfiguration management detect this request and initiate its statemachine to fill the correct registers for the transceiver reconfiguration controller with data. 

- the data that is been written correspond with MIF Mode 1 direct write reconfiguration from the xcvr_user_guide chapter 16-37 (direct write reconfiguration) 

- the statemachine in the reconfiguration management however waits at a certain point until the reconfig_busy signal from the transceiver reconfiguration controller but this signal stays low eternally. 

i would assume that the reconfig_busy signal would go high as soon as the mif mode registers are correctly set? and goes low when the reconfig is done as shown in the datasheets.  

 

So my question is there anybody who has a working SDI II Rx design which can give me some pointers because i don't have a clue what goes wrong...  

 

Thanks in advance
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3 Replies
Altera_Forum
Honored Contributor I
40 Views

Hi, did you ever sort this out? I'm having a similar issue. Thanks, I appreciate it!

Altera_Forum
Honored Contributor I
40 Views

Hi DRC,  

 

After all on my side it was very easy to solve. I did not check the checkbox "enable channel/PLL reconfiguration" in the transceiver reconfiguration controller. this item automatically checks "Enable PLL reconfiguration support block" which is ok! All the other checkboxes are unticked except for the "enable analog controls" 

 

I hope this helps to solve your issue.
Altera_Forum
Honored Contributor I
40 Views

Thank you! That worked.

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