HiI want to implement the SDI megacore IP in CYCLONE IV GX devices and I have the following concerns: 1- according to the use SDI megacore user guide (Page 3-27), it does not support MIF generation for EP4CGX30,50,75. Does this mean I need to use and old version (older than 10.1) 2- Is the receiver able to automatically lock to 1/1.001 rates without a 1/1.001 reference clock being provided? (ie. ref clock = 148.5 but SDI rate = 148.35) I would appreciate it if someone could give me some info. Thanks,
Am half way thru this, hoping someone will share too. The whole IP-SDI core seems to be put together in an ad-hoc basis, with a lot of confusion and 'misleading' information in the user guide.
Yup, it seems that I am forced to be packing up, and moving back to Xilinx camp, and throwing away a lot of fully populated board into the sea because of some useless and restrictive core.
--- Quote Start --- I would like to hear comments to this criticism from Altera officials. --- Quote End --- Haha....I did got some comment from Altera 'Officials' from other channel, but I cannot disclose the discussion...:)
--- Quote Start --- I wish I could give up, like you. Now, the deeper I dig, the more bugs, misrepresentations, and undocumented requirement starts to appear. --- Quote End --- Did anyone successfully used Altera SDI IP?