FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

SGDMA dropping two bytes just before (not at) end of transfer

Altera_Forum
Honored Contributor II
988 Views

I'm having problems with an SGDMA controller connected up to a TSE ethernet MAC. It's a 32-bit memory to stream SGDMA set to accept misaligned transfers. 

 

I'm trying to transmit a packet produced by the LWIP stack, which basically gives me a 42 byte header data array, and another array for the packet data. I set up a chain of two descriptors, one that sends the 42 bytes of header, chained to another that sends the data. 

 

When I run the transfer, I expect the output to be: 

{h[0], h[1], ..., h[40], h[41], d[0], d[1],..., d[n]} 

(h[] is the header, d[] is the udp packet data) 

 

But looking at the output on Ethernet and on the SGDMA's Avalon-ST output, I'm actually getting: 

{h[0], h[1], ..., h[34], h[35], h[38], h[39], h[40], h[41], d[0], d[1], ..., d[n]} 

 

I can't find any documentation on the behavior of the SGDMA when doing a transfer like this, or any description of what you're allowed/not allowed to do, or any example waveforms. 

 

Is it allowed to have transfers that are not multiples of 4 bytes length when the data width is 32 bit? Is there any documentation that has the info I need? 

 

Regards, 

David
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
254 Views

Maybe the problem connected with 32-bit allignment. try to turn it off. 

For example for TSE align packet headers to 32-bit boundaries cuts first 2 bytes during the transmiting.
0 Kudos
Altera_Forum
Honored Contributor II
254 Views

It's been a while but I did a lot of early work with the TSE MAC and helped isolate some issues with it. I remember trying to get the SGDMA controllers to properly perform unaligned data transfers in conjunction with the TSE MAC but never could get it working. As dim99 mentioned, the TSE megawizard has an option to align the packet headers to 32-bit boundaries to avoid the need for unaligned transfers at the SGDMA controller. 

 

Jake
0 Kudos
Reply