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I'm using the sgdma with 32-bit aligned read buffers as recommended but I still get corrupted read data. I haven't found any known issues about 8-bit operation. Does anyone know if 8-bit operation works? It seems to work for many transfers but not all as if the starting address affects it.
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--- Quote Start --- I'm using the sgdma with 32-bit aligned read buffers as recommended but I still get corrupted read data. I haven't found any known issues about 8-bit operation. Does anyone know if 8-bit operation works? It seems to work for many transfers but not all as if the starting address affects it. Thanks --- Quote End --- What interface are you transferring the data over? I had terrible problems with holes in DMA'd data (from my dma engine) across the PCIe bus in Q 11.X with a memory mapped avalon interface. Q12.0 fixed the problem (although the Q12.0 qsys component editor's badly broken so I'd recommend Q12.1 ). Nial
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If the data is coming from, or being verified by, a nios cpu, are you sure the data cache isn't affecting things?
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GZoinker - Thanks for the suggestion. I was monitoring the read data directly (via SignalTap) going into the DMA so I know the data is bad from the start.
dsl - I think you may have got the answer! I'll check it out. Thanks!- Mark as New
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Everyone gets caught out by the lack of cache coherency!
(except those of us who only use tightly coupled memory and no data caches)- Mark as New
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Thanks dsl, clearing the cache has cleared things up!
Cheers Greg
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