SPI4 Loop Back Design on STRATIX III Development board
This design archive has POS PHY Level 4 (SPI4.2) STRATIX III reference design. It performs loop back test transporting packets from SPI4 TX to SPI4 RX. SPI4 RX has 1KB, 16-port shared buffer with 64 bits Atlantic interface. SPI4 TX has 1KB, 16-port shared buffer with 128 bits Atlantic interface.
The design transmits and receives billions of packets without problem. To use it, simply open top.qar and compile the design. To port the design to your board, you might want to change to speed grade according to STRATIX III on board.
Open the stp1.stp and Spf1.spf to run the system. SignalTap file stp1.stp monitor link up rdat_sync, error handling, and packet counter. SourceProbe file Spf1.spf can launch the run by toggle the reset_n to reset the STRATIX III. It also provides error injection and error recovery control in SOURCEPROBE spf1.spf.
Step by step quick start:
- Open the top.qar and recompile module top.
- open the stp1.stp and spf1.spf
- Program the top.sof file onto STRATIX III Development board after power on
- Reset with reset_n of spf1.spf
