Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,102 Views

Sata 2.0

Hi, 

I'm (quite) new about forum. Sorry if my post is not in the correct section. 

I'm working to design a Sata controller. I'm using a Cyclone V 5CGX. I started to develop a preliminary draft of the design with command, transport and link layer. Now I need to insert the phisical layer. I would like to understand what should be the best way to approch the configuration of transceiver PHY to support Sata protocol. Is better to start from Custom PHY IP Core as stated in V-Series Transceiver PHY IP Core User Guide or to start with Cyclone V Transceiver Native PHY? I found only one document about Sata/SAS protocol implementation and it is AN635 Implementing SATA and SAS Protocols in Altera Devices. But, unfortunately, this document is related to old device and old version of Quartus. I tried to move the transceiver configuration found in this application note to MegaWizard in Quartus 16.0 with Native PHY. Is a good way to proceed? Is there any other application note similar to AN635 for Cyclone V family device? 

 

Thank you in advance, 

Gabriele
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
35 Views

Further question: if in Cyclone V Transceiver Native PHY is set Standard PCS/PMA interface width 20, and consequently FPGA fabric/PCS interface is set automatically to 32, why in the generated wrapper I find 

 

tx_parallel_data : in std_logic_vector(43 downto 0) and 

rx_parallel_data : out std_logic_vector(63 downto 0) ? 

 

I should expect 32 bit interface. Which others parameters I need to set to have 32 bit FPGA/PCS interface? 

 

Best regards, 

Gabriele
Reply