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Should the top and bottom hard memory controllers in Cyclone V FPGA be clocked from separate reference clock pins? When I try to use a single pin Quartus complains that the PLLs are clocked from a global clock network and timing analysis may not be valid.


From reading various documents and the position of the 8 PLLs in the 5CEFA9F31C7 device I am using and their connection to physical clock pins there is no way to provide the reference clock input to both the top and bottom hard memory controllers from a single clock pin. Is this correct, or am I missing something?

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Hi Sir,


Yes, you are right. There is a dedicated clock input pin to the GCLK network as shown below. For the clock input pin connection to GCLK, you may refer to Table 4-2 under "Chapter 4 Clock Networks and PLLs in Cyclone V Devices" --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf




In the handbook also mentioned that driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not be able to fully compensate for the global or regional clock. Intel recommends using the CLK<#>p pins for optimal performance when you use single-ended clock inputs to drive the PLLs. 


Hope this helps.