SigTest 6.1.06 CLI TIE Error Message Unclear

[pragathi_venkatesh]

Hi all, I'm running into an error where my test runs successfully when using the GUI but not the CLI.

I ran the following in powershell: 

PS C:\Program Files\SigTest 6.1.06> .\SigTest.exe PCIe 6_0 "Base_TX_w_52UIJitterPattn" /wf "C:\Users\PragathiVenkatesh\Downloads\64G_52uijitter_d_Run000_no_deembed.bin" /xn /t 5dB_CTLE
PS C:\Program Files\SigTest 6.1.06> Test in progress, please wait......
Test has finished successfully.
Exception happened during test. Please check the log file for detailed information

It looks like the test ran successfully, but something happened when trying to create the report files/output files.

Has anyone come across this issue before? I've attached the error message log, but it isn't a very helpful error message.

Thank you,
Pragathi

[pragathi_venkatesh]

Note: I also get the same error message when specifying an output file path: .\SigTest.exe PCIe 6_0 "Base_TX_w_52UIJitterPattn" /wf "C:\Users\PragathiVenkatesh\Downloads\64G_52uijitter_d_Run000_no_deembed.bin" /xn /t 5dB_CTLE /o ~/Downloads/test.out

[Wincent_Altera]

Hi ,

May I know which device that you are using ? Is it altera device ?

What software that you to test the sigTest ?

Regards,

Wincent_Altera

[pragathi_venkatesh]

Hi Winent! I'm using a Windows 10 x64-based PC. I've tried this with SigTest 6.1.06 and 6.1.09 but run into the same issue. I use powershell to run automated tests.

[pragathi_venkatesh]

Wincent* Apologies

[Wincent_Altera]

Hi ,

May I know which design that you are using to perform the Sigtest ?

What is the FPGA device that you are using ? Agilex 7 device ? R-tile ?

Regards.

Wincent_Altera

[pragathi_venkatesh]

Right now, we use a Keysight BERT (or equivalent pattern generator) to send the 52UI PCIe6 jitter compliance pattern. 

[Wincent_Altera]

Hi ,

May I know which device that you are using to run the test ? Agilex 7 device ? R-tile or P-tile ?
Above question is important for me in other to define an accurate answer towards your issue.
As far as I know Altera is not yet launching gen6 solution at the moment. 

we use a Keysight BERT (or equivalent pattern generator) to send the 52UI PCIe6 jitter compliance pattern. 
>> It seen to me like there is not related to Altera product, do you trying to reach out to Keysight support ?

Regards,
Wincent_Altera

[pragathi_venkatesh]

The issue is that the test runs successfully when using the SigTest GUI but fails when using SigTest CLI. This means the issue is with the SigTest CLI usage, and I'd like to know what the correct CLI arguments are.

[Wincent_Altera]

Hi @pragathi_venkatesh ,

Can I please get your confirmation on below question ? 
"May I know which FPGA device that you are using to run the test ? Agilex 7 device ? R-tile or P-tile ?
Above question is important for me in other to define an accurate answer towards your issue.
As far as I know Altera is not yet launching gen6 solution at the moment. "

IF you are not using any FPGA device, Perhaps you shall go to Intel community as this is out of our suppose scope in this forum (FPGA forum)

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

As mentioned, if you are not using any Altera FPGA device, I suggest you to post the question in "Intel forum" page.

Hope the right expert will connected to you soon. Let me know if you have further question.

Regards,

Wincent_Altera