Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]

[ALMSlinger]

Hello,

I am using pld_clk as signaltap clk to sample the test_out[319:0] signals of the pipe interface in Arria10GX HIP.  But on the board the signaltap complains that pld_clk was not found.  This happens even after the board enumerates successfully.  

How do capture test_out in signaltap?

Thank you.

Best regards

[Wincent_Altera]

Hi,

I am not sure if there is any special requirement on your current project.

But normally I will use use coreclkout_clk as the sample of signal.

But on the board the signaltap complains that pld_clk was not found. 

>> can you please show me your signal tap printscreen ?

This happens even after the board enumerates successfully.  

>> is it the ltssm able to link up ?

Regards,

Wincent_Intel

[ALMSlinger]

Wincent,

1. The test_out signals are the pipe interface signals.  I need to see what is coming out of the MAC/PCS sublayer. 
2. The test_out to coreclkout is across clock domains.  You can see this from the timing analyzer report.  Please see the picture.
3. I do not have a picture of signaltap where it complained that the sampling clock was missing.  But the screen shot of the signaltap screen is attached.
4. Yes! LTSSM enters L0 state.

I have attached the Arria 10 GX dev board example design project with this signal tap.  Please check the attached zip file.

 

 

[Wincent_Altera]

Hi,

Kindly find the updated FTA for the PCIe debugging which is available in Intel Website .

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

>> click on Debug

1. In the 4th tab of the spreadsheet, it says to use test_out to observe PCIe PIPE interface signals. 
2. you can refer to the 'Diagram' tab in the PCIe FTA excel sheet, which shows a screen shot of 'Expected behaviour for rxstatus, phystatus, txelecidle, txdetectrx' as an example.
3.  

For the test out signal, you can ignore it , for the test_in, you should focus on the PCIe IP top level signal, which is 32bit , you can refer to the user guide about it

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01145_avmm-1_0.pdf

Hope that able to help you to move forward.

Regards,

Wincent_Intel

[ALMSlinger]

Thanks Wincent for digging this out.  I had seen this before.  Unfortunately, the spreadsheet doesn't say which clock to use to sample test_out.  I don't undersand what you mean by ignoring the test_out signal.  I want to see what is on the following signals.

So I am asking again - what clock should I use in signaltap to sample these signals?

rxvalid0	1	test_out [86]	test_out [246]
rxblkst0	1	test_out [85]	test_out [245]
rxsynchd0	2	test_out [84:83]	test_out [244:243]
rxdataskip0	1	test_out [82]	test_out [242]
rxdatak0	4	test_out [81:78]	test_out [241:238]
rxdata0	32	test_out [77:46]	test_out [237:206]
powerdown0	2	test_out [45:44]	test_out [205:204]
rxpolarity0	1	test_out [43]	test_out [203]
txcompl0	1	test_out [42]	test_out [202]
txelecidle0	1	test_out [41]	test_out [201]
txdetectrx0	1	test_out [40]	test_out [200]
txblkst0	1	test_out [39]	test_out [199]
txsynchd0	2	test_out [38:37]	test_out [198:197]
txdataskip0	1	test_out [36]	test_out [196]
txdatak0	4	test_out [35:32]	test_out [195:192]
txdata0	32	test_out [31:0]	test_out [191:160]

Thank you for the help.

Best regards,

Sanjay

[Wincent_Altera]

Hi,

I am unable to trace the .stp file, can you please attach the .stp file separately here ?
normally for pcie cases, we suggest to use either

1. dut_coreclkout_hip_clk

2. dut|dut|altpcie_a10_hip_pipen1b|coreclkout

3. if not solved maybe you can try out using pld_clk

Can you please try it and get back to me for your result ?

Regards,

Wincent_Intel

[ALMSlinger]

Hi Wincent,

According to this timing analyzer report, clocking signaltap with coreclkout will create clock transfers between test_out and signal tap nodes.  The test_out is being clocked out by pld_clk.  The problem is that signaltap complains that PLD_CLK is not running even after PCIe end point successful enumerates. 

Do we need to write any value on test_in bus to make the pld_clk run?  The stp file is called pcie_dbg.stp in the zip file that I attached early on in the post.  Let me know if you have trouble accessing it.

Thank you.
Best regards,

Sanjay

[Wincent_Altera]

Hi,

By right you should be able to use the coreclkout_hip as a signal tap sampling clock. 

As a start, you can set the trigger on ltssm transition (this is done and confirm by you in previous command),  by right you should able to see corresponding signals in the test_out bus.
I check with our internal team, timing violations with the test_out bus is ok, as this interface is purely debug interface.

The problem is that signaltap complains that PLD_CLK is not running even after PCIe end point successful enumerates. 
>> If you need to remove timing errors, maybe you can try to synchronizing the deassertion of nPor to free running 1000Mhz clock to avoid plc_clk not running after pcie endpoint success enumerate
>> I dig deeper into the altpcie_a10_hip_pipen1b.v module and found that nPor is being used straight up as a reset on various registers in the pld_clk domain
>> my understanding that Npor resets the entire IP Core and transceiver.
>> Reset logic like PERSTn, nPor and/or local_rstn are written in Verilog at top level file.

Maybe you can try that and see if you are able to get it up.
Let me know if you still have any concern, Apology that I never try this till so deep, but I will try my best to assist you.

Regards,
Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[Wincent_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.

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The community users will be able to help you on your follow-up questions.

Nevertheless, you can still response to the case to reopen anytime within 20 days, and I will be available to assist you.

Rest assured, even after the ticket is closed, we will continue to keep you informed of any developments until the issue is resolved..

We appreciate your understanding and we are committed to assisting you with any further questions.

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Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.