Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]

[ALMSlinger]

Hello,

I am using pld_clk as signaltap clk to sample the test_out[319:0] signals of the pipe interface in Arria10GX HIP.  But on the board the signaltap complains that pld_clk was not found.  This happens even after the board enumerates successfully.  

How do capture test_out in signaltap?

Thank you.

Best regards

[wchiah]

Hi,

I am not sure if there is any special requirement on your current project.

But normally I will use use coreclkout_clk as the sample of signal.

But on the board the signaltap complains that pld_clk was not found. 

>> can you please show me your signal tap printscreen ?

This happens even after the board enumerates successfully.  

>> is it the ltssm able to link up ?

Regards,

Wincent_Intel

[ALMSlinger]

Wincent,

1. The test_out signals are the pipe interface signals.  I need to see what is coming out of the MAC/PCS sublayer. 
2. The test_out to coreclkout is across clock domains.  You can see this from the timing analyzer report.  Please see the picture.
3. I do not have a picture of signaltap where it complained that the sampling clock was missing.  But the screen shot of the signaltap screen is attached.
4. Yes! LTSSM enters L0 state.

I have attached the Arria 10 GX dev board example design project with this signal tap.  Please check the attached zip file.

 

 

[wchiah]

Hi,

Kindly find the updated FTA for the PCIe debugging which is available in Intel Website .

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

>> click on Debug

1. In the 4th tab of the spreadsheet, it says to use test_out to observe PCIe PIPE interface signals. 
2. you can refer to the 'Diagram' tab in the PCIe FTA excel sheet, which shows a screen shot of 'Expected behaviour for rxstatus, phystatus, txelecidle, txdetectrx' as an example.
3.  

For the test out signal, you can ignore it , for the test_in, you should focus on the PCIe IP top level signal, which is 32bit , you can refer to the user guide about it

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01145_avmm-1_0.pdf

Hope that able to help you to move forward.

Regards,

Wincent_Intel