- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi all,
I generated a QDR II Controller with UniPHY. After compiled the sources generated by mega wizard (verilog and systemVerilog), the top (vhdl) and the testbench (vhdl), I tried to simulate them with ModelSim. It appears some "funny" errors: ** Error: Unresolved defparam somewhere.# Region: /test_qdr_tb/test_qdr_inst/qdr_master_altera_0/controller_phy_inst# Loading work.qdrii_mem_model# ** Error: Unresolved defparam somewhere.# Region: /test_qdr_tb/qdrii_mem_model_inst# Error loading design All the parameters in those files are define. Is someone already had this error ? ThanksLink Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi all,
I finally resolve the errors ! The error was due to the VHDL altera libraries for this controller. I used now the verilog libraries and it works fine. I reported to Altera.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page