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AKhan15
Beginner
973 Views

Simulating SCFIFO in modelsim

Hello,

 

I am new to HDL and embedded systems in general so i apologise for asking a dumb question.

 

I created the SCFIFO from the intel IP core. I only used the asynchronous clear, data, q, read and write request. No other flags were needed for my work. I imported the generated verilog files into modelsim. I then created a test bench to drive those signals as you can see below.

I compiled this using the altera_mf and 220model libraries. When, i tried to simulate it, the q (output read data) is high impedance which would suggest that nothing is connected to it, even though it did the port assignments.

Can you please advise me what am i doing wrong?

 

Thank you

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4 Replies
AKhan15
Beginner
60 Views

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Vicky1
Employee
60 Views

Hi,

Please provide below details,

  1. have you come across any error while simulation? provide log file/ transcript.
  2. provide screenshot of simulation window.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

60 Views

Hi,

 

your testbench seems correct. so possible issues are.

  1. library files are missing in simulation, it need to be added to vsim command.
  2. connections to fifo in the top level wrapper file is broken.

You can share some more details as @Vicky​  suggested for us to further take a look.

 

At same time take a look at the simple tutorial for setting up simulation with Native link setup (where all the simulation scripts are handled by quartus), hopefully you will be able to proceed.

https://www.youtube.com/watch?v=PmVVXQchv2c

 

Let us know if you have any questions.

 

Arslan

 

AKhan15
Beginner
60 Views

Thanks for the reply.

 

I think, i've solved the problem. The asynchronous clear in the IP seemed to mess things up. I tried the variant without one and everything was fine.

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