I am new to HDL and embedded systems in general so i apologise for asking a dumb question.
I created the SCFIFO from the intel IP core. I only used the asynchronous clear, data, q, read and write request. No other flags were needed for my work. I imported the generated verilog files into modelsim. I then created a test bench to drive those signals as you can see below.
I compiled this using the altera_mf and 220model libraries. When, i tried to simulate it, the q (output read data) is high impedance which would suggest that nothing is connected to it, even though it did the port assignments.
Can you please advise me what am i doing wrong?
Please provide below details,
(This message was posted on behalf of Intel Corporation)
your testbench seems correct. so possible issues are.
You can share some more details as @Vicky suggested for us to further take a look.
At same time take a look at the simple tutorial for setting up simulation with Native link setup (where all the simulation scripts are handled by quartus), hopefully you will be able to proceed.
Let us know if you have any questions.