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Simulation of seriallite II IP core on quartus II




My problem lies in the emulation of the seriallite II IP core. When I use quartus to build the project as shown in the figure, write test files, and call modelsim for simulation, the signals in my oscillogram are always wrong.


The specific error is: no matter how I change the value of each input signal, the output signal txout is always the same, and the txrdp_dat output is always 0. Even after changing the input of the reset button, the output signal will not change.


I know that there must be an error in the input signal I set, but I have tried many combinations of input signal value and frequency, and also read the manual of the seriallite II IP core, but I still haven’t figured out the correct input of each signal(such as reset and clock).


Hereby ask for help, thank you. 

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As I understand it, you have some inquiries related to bringing up the SL II IP. Just to check with you if you have had a chance to perform a functional simulation with your design prior to hardware testing? This would be helpful to isolate functional problem.

For your information, it is recommended for you to refer to the example test bench generated by the IP as discussed in "SerialLite II IP Core Testbench" section in the SL II IP user guide. After you have managed to run simulation with the test bench, you can customize it step by step to your target implementation. After you are done with the simulation, then only you move to hardware.

As I look into your BDF, I notice that you are connecting the txrdp_dat[7:0] to physical input pins. Just to check if you are feeding any data to this? To ease the debugging, you can connect the txrdp_dat[7:0] to constant data. You can drive constant data directly at RTL.

I am assuming that you have connected all the clocks ie trefclk1, cal_blk_clk1, reconfig_clk1 directly to stable and free-running oscillators on-board. Please help to verify this.

Please let me know if there is any concern. Thank you.

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