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SMS
Beginner
425 Views

Soft LVDS IP core bitslip

I am using Max10 and included Soft LVDS IP core for data transmission and reception. For link training I sent 8'h0F. Now, the data at LVDS Rx slips every clock cycle.

LVDS_IP_core_bitslip_(ext_pll).PNGI have tried to align it using the rx_data_align but that does not resolve the issue. LVDS IP was configured as:

General:

Power Supply Mode: Single Supply (for 10M16SAE144I7G)

Functional Mode: Rx

No. of channels: 1

SERDES factor: 8

 

PLL Settings:

Use external PLL (checked)

 

Receiver Settings:

Enable bitslip mode (checked)

Bitslip rollover value: 1

 

I have also tried to use internal PLL in which case the the bitslip occurs at random intervals. Now how can I fix this issue?

LVDS_IP_core_bitslip_(int_pll).PNG

 

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3 Replies
IDeyn
New Contributor III
109 Views

Hi SMS,

 

It is a strange behaviour - in case align is stable you shouldn't get bitslip as it is on first figure.

 

You could attach your project in order for community to check it.

 

--

Best regards,

Ivan

SMS
Beginner
109 Views

Attached are two projects one for Tx and one for Rx. I am programming the DE10-Lite board (10MDAF484C7G) as Tx and a custom board (10M16SAE144I7G) as Rx.

IDeyn
New Contributor III
109 Views

Hi SMS,

 

I quickly checked your project and I can say that you should begin with a creation of constraint file (sdc).

 

You should start with create_clock command, FE create_clock -name {I_ADC_FCO} -period 20.000 -waveform { 0.000 10.000 } [get_ports {I_ADC_FCO}]

 

After that and after successful timing analysis you should test if your design works.

 

--

Best regards,

Ivan

 

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