Some ploblems about PCI core

[Altera_Forum]

I want to implement a 5v 32-bit PCI target in EP2C35 (with PCI compiler 8.0), but the computer just hung up after plug the card in motherboard. 

1. The CyclonII devices support PCI. Does that mean I can connect PCI signals from the socket to FPGA directly? Or, should I transit them through some level-shift functions? After reading some reference design schematics, I think the 5V PCI signals should be transmitted to 3.3v with QS3861. That is the way I did on my board. 2. Should I set the IO standard to PCI or 3.3v LVTTL in quartus?  3. Anything else I have forgotten?  Any sugestion will be appreciated. thx

[Altera_Forum]

Enabling PCI I/O enables the clamping diodes in the I/O cell.  

 Be careful though as Cyclone 2 is not 5V tolerant - you will have to use some sort of level shifter between the FPGA and PCI edge connector. Therefore you probably wouldn't necessarily need the clamping diodes enabled on the FPGA  Cyclone 2 will drive 5V logic from its 3.3V I/O but most of the PCI signals are bi-directional so you will need level shifters for the majority of the signals.  You will need to set tco, tsu, th and tpd constraints when you compile the design. If these aren't met then you will get problems on your card.  The PCI spec is quite specific on trace length of the signals so be careful when you lay out your board.

[Altera_Forum]

1. I used QS3861 as level shifter, so I don't need to set PCI IO mode, it that right? 

2. Can I use the constraints script (shipped with PCI compiler) to set the time constraint? btw, my pin allocation is different from the script, is that a problem?   thx

[Altera_Forum]

1. I don't see why you should have to enable the clamping diodes if you've got a level shifter in between the FPGA and PCI bus. 

 2. I haven't used a recent version of the PCI core but by the sounds of it you don't need to set constraints manually. Does the script assign exactly the same timing constraints to each pin? - if so then moving the pins shouldn't matter from this point of view.  However it could be a board problem - timing, signal integrity etc.  Much more fundamentally how does the QS3861 handle the bi-directional signals - do you have to pass it some sort of control signal to do this?does the PCI compiler handle this?