I would like to use E-TILE transceiver reference clock input for clocking core logic bypassing transceiver.
In "Intel® Stratix® 10 Device Family Pin Connection Guidelines" document in Table 18 in REFCLK_GXE description it is written that this should be possible:
"REFCLK_GXE can be used as dedicated clock input pins for core clock generation even when the transceiver channel is not available. "
However when trying to clock core logic using reference clock I get an error:
"Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core. HSSI REFCLK divider "ref_clk_in0~inputFITTER_INSERTED" has core fanouts. "
What should I do to be able to use E-TILE reference clock for clocking core logic?
May I know which Quartus version that you used ?
I checked out Etile transcevier PHY user guide doc but didn't find any usage explanation on refclk connection to FPGA core logic.
I believe maybe it's impossible to connect Etile refclk to FPGA core.
Thank you for your answer.
I'm using Quartus 19.3.
I know that Etile transceiver PHY user guide does not contain any information regarding refclk connection to FPGA core logic.
But Intel® Stratix® 10 Device Family Pin Connection Guidelines document does have this information:
Please see page 42, Table 18.
That is why I'm asking.
I have clarified with Intel internal team.
Unfortunately E-tile refclk doesn't support direct connection to FPGA core logic as I suspected earlier.
My recommendation is as below
I have not hear back from you for close to 1 month.
Hopefully my earlier explanation is clear to you.
For now, I am setting this case to closure.
Feel free to post new forum thread if you still have new enquiry in future.