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Stratix 10 E-TILE reference clock

MUrba10
Beginner
395 Views

Hello,

 

I would like to use E-TILE transceiver reference clock input for clocking core logic bypassing transceiver.

 

In "Intel® Stratix® 10 Device Family Pin Connection Guidelines" document in Table 18 in REFCLK_GXE description it is written that this should be possible:

 

"REFCLK_GXE can be used as dedicated clock input pins for core clock generation even when the transceiver channel is not available. "

 

However when trying to clock core logic using reference clock I get an error:

 

"Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core. HSSI REFCLK divider "ref_clk_in0~inputFITTER_INSERTED" has core fanouts. "

 

What should I do to be able to use E-TILE reference clock for clocking core logic?

 

Thank you!

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4 Replies
Deshi_Intel
Moderator
358 Views

Hi,

 

May I know which Quartus version that you used ?

 

I checked out Etile transcevier PHY user guide doc but didn't find any usage explanation on refclk connection to FPGA core logic.

 

I believe maybe it's impossible to connect Etile refclk to FPGA core.

  • This could be wrong explanation on Intel® Stratix® 10 Device Family Pin Connection Guidelines table 18.
  • Anyway, pls let me clarify with Intel internal team first then I will get back to you.

 

Thanks.

 

Regards,

dlim

MUrba10
Beginner
358 Views

Hello,

 

Thank you for your answer.

 

I'm using Quartus 19.3.

 

I know that Etile transceiver PHY user guide does not contain any information regarding refclk connection to FPGA core logic.

 

But Intel® Stratix® 10 Device Family Pin Connection Guidelines document does have this information:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf

 

Please see page 42, Table 18.

 

That is why I'm asking.

 

Thank you!

 

Best regards,

Mikhail

Deshi_Intel
Moderator
358 Views

Hi Mikhail,

 

I have clarified with Intel internal team.

 

Unfortunately E-tile refclk doesn't support direct connection to FPGA core logic as I suspected earlier.

  • This is a explanation mistake in S10 pin connection guide doc. We will fix and update the doc accordingly

 

My recommendation is as below

  1. If you insist of using E-tile refclk then you can choose to configure E-tile NativePHY in PLL mode where it convert one of E-tile transceiver channel into PLL that can be used to clock FPGA core logic. Refer to chapter 2.2.11 PLL mode
  1. Else you can also use any IOPLL refclk pin or any IOPLL output clock to clock FPGA core logic

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
355 Views

Hi Mikhail,


I have not hear back from you for close to 1 month.


Hopefully my earlier explanation is clear to you.


For now, I am setting this case to closure.


Feel free to post new forum thread if you still have new enquiry in future.


Thanks.


Regards,

dlim 



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