I am using L-tile S-10 SoC dev kit and using native PHY IP for transceiver interface.
I want to switch the data rate between 10G and 20G using dynamic reconfiguration. Here, both Native PHY and ATX PLL must be reconfigured as the serial clock varies for targeted data rates. However, reference clock frequency remains same (156.25MHz).
Any example design is available for stratix 10 L-tile dynamic reconfiguration?
As I understand it, you have some inquiries on S10 L Tile dynamic reconfiguration example design. For your information, as I search through the internal database, it seems like there is no specific design on this. However, you can try to refer to the C10GX dynamic reconfiguration at the following link as reference:
Note that this design is using ATX PLL switching and channel reconfiguration. You need two ATX PLLs but does not need to perform ATX PLL reconfiguration.
Please let me know if there is any concern. Thank you.
I downloaded the above example design and opened in the quartus. The top file is a .bdf file where I am seeing the reconfiguration ports are not connected to any controller. In this project, who will control the reconfiguration ports?