Stratix 10 M20K Clock Clock Enable for ECC Pipeline register

[LennartVH]

Hi there,

In the M20K documentation on ECC, there is mention of an optional pipeline register within the ECC pipeline for achieving higher FMax. It is not entirely clear if adding a clock enable to the output register also adds a clock enable to this internal register.

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/error-correction-code-truth-table.html

https://www.intel.com/content/www/us/en/docs/programmable/683240/17-0/ram-and-rom-parameter-settings.html

What I want to get is a M20K block where the read addr, ECC pipeline register and output register all have a clock enable. So that reading takes 3 clock enables to complete.

Does adding a clock enable to "all output registers" add a clock enable to the internal ECC pipeline register?

Another minor question, why is it seemingly impossible to add a clock enable to the M20K output register in single-clock dual-port mode? I can only either add a clock enable to all ports, or to none of them, but in dual-clock mode this is not a problem?

One final thing, what does clock_enable_core_b: "The clock enable for the core of port B." this mean? The 'core' of port A/B?

Kind regards,
Lennart

[SyafieqS]

Hi Lennart,

Let me check this information internally and will be back with update.

[SyafieqS]

Hi Lennart,

I was on long holiday thus expect some delay in update.

[LennartVH]

Hi SyafieqS,

Thank you for your time. This is still an open question for us. As our build system is broken right now I can't test it myself, so having confirmation on how the M20K output registers work would really help.

Kind regards,
Lennart

[LennartVH · Accepted solution]

In the end I was able to test that yes indeed, applying a clock enable to the output registers does add a clock enable to the pipeline registers as well.

As for the other questions, they're still a mystery, but at least we can continue development with this.

[SyafieqS]

Lennart,

Noted. Let me know if there is any other concern.