Stratix 10 serial flash mailbox client IP clarification

[Scotty2]

Hello,

I am quiet new to the Intel and Stratix 10 environment, so pardon me if this is a trivial post. If I need to post this somewhere else, do let me know!

I am trying to wrap my head around updating a QSPI once one has booted into the HPS Linux environment (in HPS first boot mode). The goal is to update/read/write the QSPI flash with a new u-boot  and FPGA I/O part of the bitstream without using JTAG (not using the .JIC file)

From what I understood, to do this I need to add the "serial flash mailbox client" IP because writing directly to the flash is not possible and I have to go through this IP for the sake of making SDM happy. 

My questions are:

1. Is my understanding correct?

2. Is there an official Linux driver for this IP?

3. Is there a more direct/easy method to go about this?

4.  Assuming all of this is done, the file format that needs to be given to the mailbox is ".rpd" or ".rbf" ?

here are some of the docs I have looked at:

1. "Stratix 10 Mailbox Client Intel FPGA IP Core Design
Example(QSPI Flash Access and Remote System
Update)"

2. Design Example (intel.com)

3. Stratix 10 Mailbox Client IP Core Design Example - QSPI flash Access and Remote System Update - Intel Communities

4. tutorial-write-raw-programming-data-rpd-into-flash-devices.pdf (intel.com)

5. 9.3. Creating Application and Update Images for HPS First (intel.com)

6. 9. Using RSU with HPS First (intel.com)

7. Serial Flash Mailbox Client Intel FPGA IP User Guide

Thank you

[EBERLAZARE_I_Intel]

Hi,

I am checking the issue now, in the mean time you can take a look at below reference:

https://rocketboards.org/foswiki/Documentation/Stratix10SoCGSRD#Typical_HPS_Boot_Flow

https://rocketboards.org/foswiki/Documentation/BuildingBootloader#Stratix_10_SoC_45_Boot_from_QSPI

[EBERLAZARE_I_Intel · Accepted solution]

Hi,

Unfortunately we do not have a Linux driver for the FPGA mailbox. The alternative is using HWMON on the SDM mailbox calls. 

[EBERLAZARE_I_Intel]

Hi,

Do you have any additional questions?

[Scotty2]

Hi,

thank you for getting back to me!

well since the main purpose of the flash interaction is to update it remotely and after rereading the documentation about the RSU feature multiple times, it seems that is the way to go. The RSU client and the libraries seem to provide a application layer (user layer) method of rewriting the external memory. This way there seems to be no need to add any extra IPs to the hardware design and all is handled on the software side.

So I will be looking more into this method, and will open a new question if something comes up later  

thank you!

[EBERLAZARE_I_Intel]

Hi,

Thanks for the update, feel free to post a new questions.