Stratix10 PHY Lite IP - Output clocks

[anat]

Hi Team,

Are the additional output clocks (outclk1, outclk2, outclk3, outclk4) generated by PHY Lite IP, synchronous to each other? 

[AdzimZM_Intel · Accepted solution]

Hi

"Are the additional output clocks (outclk1, outclk2, outclk3, outclk4) generated by PHY Lite IP, synchronous to each other?"

• Yes

Regards,

Adzim