Stratix10 PHYLite: avl_readdata on Avalon Interface Always Returning 0

[vinupriya]

Hi,

I am working on a design on Stratix 10 using PHYLite to read Phylite paramater table in Quartus version 20.3.
I'm using a Nios II processor, and since it supports only 32-bit addressing, I've added the Address Span Extender (ASE) IP in the design. My ASE configuration is as follows:

I have set Base address to control register:

Window0 Cntl Address:  0000_0000_0500_0000

Window1 Cntl Address:  0000_0000_0000_0000

My ASE and PHYLite connections:

Window Slave and Cntl -> Nios II data master

Expanded master -> PHYLite avalon interface

I can see the avl_read and avl_readdata_valid pulse in signal tap but avl_readdata is always 0.

I tried reading from address range 0x500_0000 to 0x500_0078.  In all cases, the readdata is 0.

I also noticed that when avl_read is high, the avl_address shows values like 0x1400009, 0x1400005, etc., which is the corresponding word addresses for 5000024, 5000014, and so on.

Could you please help me to debug why avl_readdata is always zero. Am I missing any configuration or setup?

[AdzimZM_Intel]

Hi,

Is there any expected result from readdata signal from any address? Such as at initial address?

Maybe you can check the timing report for any timing issue. If timing issue exist in the design, you can try to fix that first.

You also can try to reduce the DQ width to create a smaller interface in PHYLite IP.

Therefore, you can connect directly to NIOS with Address Span Extender IP.

Have you verified the PHYLite IP can perform read and write transfer successfully with the example design?

Regards,

Adzim

[vinupriya]

I'm reading the PHYLite table as mentioned in the user guide. Please check the guide for more details.

It’s working fine in simulation.

However, I didn’t see any readdata from any address.

I also checked the timing report - there are no timing issues in the design

[AdzimZM_Intel]

Hi

Can you show the IP connection in the Platform Designer?

Regards,

Adzim

[vinupriya]

Shown below are the IP connections in Platform Designer.

[AdzimZM_Intel]

Hi

Which PHYLite table that you referred to? Can you provide the link to the that?

The simulation run is with a design that has NIOS + Address Span Extender + PHYLite IP?

It's possible to debug this issue without using Address Span Extender?

Maybe can try to reduce the number of group in PHYLite IP?

How do you enable the Avalon Memory Mapped Slave in PHYLite IP?

Regards,

Adzim