Hello,i am running a FFT and i want to do some calculations in the Avalon-ST chain (e.g. absolut spectrum). Therefore i have delayed the streaming control lines for that amount of clock cycles the math needs. This only works for about ~14 clock cycles latency else the SG-DMA does not work. Does anybody know why this is? Shouldn't it be equal how many clk cycles latency occur in the streaming chain? Thanks a lot!
please does anybody have an idea for the following behaviour?as soon as i integrate e.g. a 2 clk cycle D-flip flop after the FFT-core to delay all data and control lines of the streaming interface (except fft sink ready) the data of the first packets are right but the later ones are shifted (inside the packet).