FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5745 Discussions

Supporting Protocol specific presets in Stratix 10 L-tile Transceivers

HBhat2
New Contributor II
224 Views

Hi,

We are trying to interface some high speed protocol devices with Stratix 10 SoC dev kit @20gbps. 

The protocol expects the Transmit presets as shown below.

HBhat2-GRL_0-1606288515135.png

 Also, I downloaded the pre-emphasis estimator for Stratix 10 from below link.

https://www.intel.com/content/dam/www/programmable/us/en/others/literature/hb/stratix-10/stratix10_h...

My question is how to support the protocol specific presets with the help of VOD, "1st Pre-Tap Pre-Emphasis" & "1st Post-Tap Pre-Emphasis" of the stratix 10 transceivers. 

With regards,

HPB

 

0 Kudos
4 Replies
CheePin_C_Intel
Employee
198 Views

Hi HPB,


As I understand it, you have some inquiries related to the TX Analog PMA settings in the S10 Native PHY to meet your target protocol's requirement. As I look at the screenshot that you share, sorry as I am not sure how to translate the table into the exact setting in the Native PHY. As a workaround, you can try to look through the TX/RX PMA analog mode rules at the Analog PMA Settings tab to see if you can find your target protocol.


If not, you might need to explore into how to map the table's value into our S10 Native PHY settings. Sorry for the inconvenience.


By the way, what is the specific protocol that you are targeting?


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin



HBhat2
New Contributor II
195 Views

Hi,

We are targeting USB4 protocol.

With Regards,

HPB

CheePin_C_Intel
Employee
167 Views

Hi,


Sorry for the inconvenience. I might have overlooked your latest response. 


Thanks for your clarification that you are targeting USB4. As I understand it from the S10 L/H-Tile user guide, seems like there is no specific information about USB4 protocol. In other words, there is no formal support or characterization done for USB4 protocol. This could explain why there is no ready preset on this in the Native PHY.


As a workaround, you would need to perform your own evaluation on the right set of PMA analog settings to work with your target protocol as suggested in my previous note. Sorry for the inconvenience.


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin


CheePin_C_Intel
Employee
152 Views

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.



Reply