TSE generated constraints ignored

[Altera_Forum]

I am having some basic problems with the TSE core, and I'm pretty sure it has to do with timing constraints and/or the actual clocks I'm providing the to the TSE. None of the constraints in the SDC file generated by the TSE megafunction are taking affect in the compile. I get the following messages for each constraint: 

 "Warning: clk could not be matched with a keeper." "Warning: Ignored assignment: create_clock -name {clk_to_the_eth_interface_v8} -period 15.151 -waveform { 0.000 7.575 } [get_keepers {clk}]" "Warning: Argument <targets> is an empty collection"  The names of the clocks in the constraints match the names of the signals in my design, so I don't understand why it can't find them.  I have tried adding basic constraints on the clocks on the rest of my design, but it doesn't seem to change anything (I'm also very new to using timequest and do not know if I'm doing it properly). I added the following lines:  create_clock -name {CLK_base} -period 20.000 [get_ports {CLK_src}] create_clock -name {ENET_RX_CLK} -period 8.000 [get_ports {ENET_RX_CLK}] -add create_clock -period "180 MHz" -name SYS_CLK [ get_keepers CLK_base]  When I load my design onto my Cyclone III dev kit (with Marvel 88E1111 PHY), I can read and write to MAC/PHY registers, and see the RX/TX lights activate appropriately. However packets do not make it out intact (I don't see them on Wireshark), and I get alignment errors instead of valid packets in my RX FIFO.  Should I be taking the RGMII RX clock from the PHY through a pll/global routing, or just feed the signal directly into the rx_clk port on the TSE? I have tried skewing the RGMII TX (output) clock with a pll by 2ns as mentioned in other threads, but I still haven't had success transmitting packets. What are some basic constraints I should have on these RGMII signals that might solve my problems? How can I get the constraints from the TSE to not be ignored?

[Altera_Forum]

Try taking rx clock from PHY through pll with -100 degree phase shift and skew tx clock with 100 degree. Also make sure you are giving proper clock to phy as per ethernet link established (i.e. 2.5 MHz for 10Mbps, 25MHz for 100Mbps and 125 MHz for 1000Mbps). You probably need to pass tx/gtx clock to phy through a mux to select appropriate clock depending on your mode selection.

[Altera_Forum]

--- Quote Start ---  "Warning: clk could not be matched with a keeper." "Warning: Ignored assignment: create_clock -name {clk_to_the_eth_interface_v8} -period 15.151 -waveform { 0.000 7.575 } [get_keepers {clk}]" "Warning: Argument <targets> is an empty collection"  The names of the clocks in the constraints match the names of the signals in my design, so I don't understand why it can't find them.  --- Quote End ---   Is really "clk" the name of the clock in your design? I have some trouble making Timequest find the clocks sometimes to. I usually try to stick to the target with the clock comes from a pin, and ] when it comes from a pll.

[Altera_Forum]

--- Quote Start ---  Should I be taking the RGMII RX clock from the PHY through a pll/global routing, or just feed the signal directly into the rx_clk port on the TSE? I have tried skewing the RGMII TX (output) clock with a pll by 2ns as mentioned in other threads, but I still haven't had success transmitting packets. What are some basic constraints I should have on these RGMII signals that might solve my problems? How can I get the constraints from the TSE to not be ignored?  --- Quote End ---   I managed to make the gigabit ethernet working on the Cyclone III dev kit with the following: - connect the rx_clk to the TSE - use a pll to generate the 125MHz for the transmit clock: phase 0 degres for the TSE, and phase 90 degres for the phy gxt_clk. - fully constraining all the rgmii pins.  Here are parts of my SDC file. I'm not a Timequest expert either, but I managed to get the interface fully constrained using this, and the design works. You may have to change a few names in the file. #************************************************************** # Create Clock # ************************************************************** create_clock -name {clkin_125} -period 8 create_clock -name {enet_rx_clk} -period 8 # ************************************************************** # Create Generated Clock # ************************************************************** derive_pll_clocks set enet_tx_in_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk set enet_tx_out_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk # ************************************************************** # Set Input Delay # ************************************************************** set_input_delay -clock enet_rx_clk -min 1.5 enet_rx_dv}] -add_delay set_input_delay -clock enet_rx_clk -max 2.5 enet_rx_dv}] -add_delay set_input_delay -clock enet_rx_clk -clock_fall -min 1.5 enet_rx_dv}] -add_delay set_input_delay -clock enet_rx_clk -clock_fall -max 2.5 enet_rx_dv}] -add_delay # ************************************************************** # Set Output Delay # ************************************************************** set_output_delay -clock $enet_tx_out_clk -max 1 enet_tx_en}] set_output_delay -clock $enet_tx_out_clk -min -1 enet_tx_en}] -add_delay set_output_delay -clock $enet_tx_out_clk -clock_fall -max 1 enet_tx_en}] -add_delay set_output_delay -clock $enet_tx_out_clk -clock_fall -min -1 enet_tx_en}] -add_delay # ************************************************************** # Set Clock Groups # ************************************************************** set_clock_groups -exclusive -group set_clock_groups -exclusive -group # ************************************************************** # Set False Path # ************************************************************** set_false_path -from set_false_path -to set_false_path -setup -rise_from $enet_tx_in_clk -fall_to $enet_tx_out_clk set_false_path -setup -fall_from $enet_tx_in_clk -rise_to $enet_tx_out_clk set_false_path -hold -rise_from $enet_tx_in_clk -rise_to $enet_tx_out_clk set_false_path -hold -fall_from $enet_tx_in_clk -fall_to $enet_tx_out_clk # ************************************************************** # Set Multicycle Path # ************************************************************** set_multicycle_path -from $enet_tx_in_clk -to $enet_tx_out_clk -setup -start 2 # ************************************************************** # Set Maximum Delay # ************************************************************** set_max_delay -from $enet_tx_out_clk -to 20 # ************************************************************** # Set Minimum Delay # ************************************************************** set_min_delay -from $enet_tx_out_clk -to 0 The hardest part is to constrain the ddr interface. I'm still not sure I'm doing it right here, but now that it works, I don't want to change it ;)  I'm still amazed that Altera isn't providing a reference design for the Ethernet interface on this development kit... I lost a tremendous amount of time on this (but on the other hand I learned a lot about Timequest!)

[Altera_Forum]

Just a couple bits I can answer, with the 'I'm not an expert' disclaimer: 

  --- Quote Start ---  ..."Warning: clk could not be matched with a keeper."  --- Quote End ---   The warning you're getting is due to get_keepers, which will only find node names that don't get synthesized away. Simply define the rx & tx clocks using port names from the top-level, as shown by daixiwen.   --- Quote Start ---  ...Should I be taking the RGMII RX clock from the PHY through a pll/global routing, or just feed the signal directly into the rx_clk port on the TSE?  --- Quote End ---  The rx_clk pin can be directly fed to the TSE, no need for a pll.

[Altera_Forum]

I was able to get things working after using a modified version of those timing constraints and following some of the suggestions here. Thank you!

[Altera_Forum]

Daixiwen 

  can u give ur personal mail and phone number i have so many questions t oask u yaar  reply as soon as possible

[Altera_Forum]

I'm not very available these days unfortunately, and you'll get more and better answers by asking your questions on the forum, where more people can read them.

[Altera_Forum]

--- Quote Start ---  I managed to make the gigabit ethernet working on the Cyclone III dev kit with the following: - connect the rx_clk to the TSE - use a pll to generate the 125MHz for the transmit clock: phase 0 degres for the TSE, and phase 90 degres for the phy gxt_clk. - fully constraining all the rgmii pins.  Here are parts of my SDC file. I'm not a Timequest expert either, but I managed to get the interface fully constrained using this, and the design works. You may have to change a few names in the file. #************************************************************** # Create Clock # ************************************************************** create_clock -name {clkin_125} -period 8 create_clock -name {enet_rx_clk} -period 8 # ************************************************************** # Create Generated Clock # ************************************************************** derive_pll_clocks set enet_tx_in_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk set enet_tx_out_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk # ************************************************************** # Set Input Delay # ************************************************************** set_input_delay -clock enet_rx_clk -min 1.5 enet_rx_dv}] -add_delay set_input_delay -clock enet_rx_clk -max 2.5 enet_rx_dv}] -add_delay set_input_delay -clock enet_rx_clk -clock_fall -min 1.5 enet_rx_dv}] -add_delay set_input_delay -clock enet_rx_clk -clock_fall -max 2.5 enet_rx_dv}] -add_delay # ************************************************************** # Set Output Delay # ************************************************************** set_output_delay -clock $enet_tx_out_clk -max 1 enet_tx_en}] set_output_delay -clock $enet_tx_out_clk -min -1 enet_tx_en}] -add_delay set_output_delay -clock $enet_tx_out_clk -clock_fall -max 1 enet_tx_en}] -add_delay set_output_delay -clock $enet_tx_out_clk -clock_fall -min -1 enet_tx_en}] -add_delay # ************************************************************** # Set Clock Groups # ************************************************************** set_clock_groups -exclusive -group set_clock_groups -exclusive -group # ************************************************************** # Set False Path # ************************************************************** set_false_path -from set_false_path -to set_false_path -setup -rise_from $enet_tx_in_clk -fall_to $enet_tx_out_clk set_false_path -setup -fall_from $enet_tx_in_clk -rise_to $enet_tx_out_clk set_false_path -hold -rise_from $enet_tx_in_clk -rise_to $enet_tx_out_clk set_false_path -hold -fall_from $enet_tx_in_clk -fall_to $enet_tx_out_clk # ************************************************************** # Set Multicycle Path # ************************************************************** set_multicycle_path -from $enet_tx_in_clk -to $enet_tx_out_clk -setup -start 2 # ************************************************************** # Set Maximum Delay # ************************************************************** set_max_delay -from $enet_tx_out_clk -to 20 # ************************************************************** # Set Minimum Delay # ************************************************************** set_min_delay -from $enet_tx_out_clk -to 0 The hardest part is to constrain the ddr interface. I'm still not sure I'm doing it right here, but now that it works, I don't want to change it ;)  I'm still amazed that Altera isn't providing a reference design for the Ethernet interface on this development kit... I lost a tremendous amount of time on this (but on the other hand I learned a lot about Timequest!)  --- Quote End ---      Really thanks for the answering, but my design still does not work. I am using tse_mac in rgmii mode with 88e1111 phy device. I "connect the rx_clk to the TSE, use a pll to generate the 125MHz for the transmit clock: phase 0 degres for the TSE, and phase 90 degres for the phy gxt_clk." as you said. I am new for fpga, so i do not know how to use the SDC file. If it is necessary to add the SDC file when compiling?

[Altera_Forum]

Yes, add the sdc file to the Quartus project. You can have a look at the timequest user guide (http://www.alterawiki.com/wiki/timequest_user_guide) to learn more about sdc files.

[Altera_Forum]

--- Quote Start ---  Yes, add the sdc file to the Quartus project. You can have a look at the timequest user guide (http://www.alterawiki.com/wiki/timequest_user_guide) to learn more about sdc files.  --- Quote End ---    It does work after adding the sdc file. Thanks so much!:D