Hi All
I'm a beginner with FPGAs and this is my first project involving IP and more complex Megafunctions, so please bear with me...
I need to create gigabit Ethernet connectivity for a project, so I decided to go with the Altera TSE. I have a DK-DEV-3C120N development kit with a Marvell PHY on board (connected via RGMII).
I created the TSE block (Megawizard not SOPC) with internal FIFOs and was able to run the testbench as described in the manual.
Now, could anyone provide me with a small example on how to put together the additional logic? From reading the TSE related threads in this forum I understand that there are several issues to be aware of, but my knowledge is simply not good enough to figure out how to put that into practice.
These are the points (I think) I need clarification on:
- PHY pinout (for gigabit only) with RGMII
- PHY clocking (phase shift issue?)
- PHY reset
- MAC runtime configuration
Any hint highly appreciated! :)
Bernhard
