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TV Decoder to VGA on DE2-115 using VIP Suite

Altera_Forum
Honored Contributor II
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Hello, 

I am writing this post just to share a sample project (see the attached zip) for the DE2-115 board which grabs video frames from the onboard the ADV7180 TV Decoder and outputs them to 640x480 VGA through the ADV7123 DAC using only SoPC and the VIP suite. 

 

The DE2_115_TV example contained in the Terasic DVD, which is the only example working with PAL sources I was able to find on the internet, does not take advantage of the VIP suite, rather relies on custom verilog modules, IMHO very difficult to integrate in other designs (especially when NIOS is involved) 

 

I wasted several days in order to make it work with the VIP suite (clocked video input -> chroma resample -> ... -> deinterlacer ->clocked video output) and it was quite hard for me to find enough documentation to configure properly the timing parameters of the clocking video I/O and the correct sequence for decoding ITU-R.656 to RGB. 

 

I am sharing this project (which works correctly with both PAL and NTSC sources) with the hope that it will help someone else in the future that encounters the same problem as mine. 

 

Note: this example uses the SDRAM memory for keeping the 640x480 RGB frame-buffer. I have another working variant which uses the smaller SRAM (2 Mb) for the FB, downsampling the captured frames to 320x240 and then upsampling to 640x480 before the video_output. Feel free to contact me if you need it. 

 

Regards, 

Primiano
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Altera_Forum
Honored Contributor II
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> Do you have an idea what is the maximum clock we can use in the vip suite components? 

 

There are some numbers on the user guide but they might not be very relevant since fMax will depend on the parameterization. 

The deinterlacer in high quality mode will most probably NOT run at 150MHz on CycloneIII. The frame buffer should just about make it. Other cores should be able to do more than that in general so it would be a bit surprising if you were having issues there. 

 

It is often necessary to use pipeline bridges on the Avalon-MM memory bus to get the SOPC Builder fabric to meet timing.
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Altera_Forum
Honored Contributor II
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HI, 

Thanks I think I was expecting too much from cyclone III.I am redoing all my designs with downclock.. 

If you know there is a link with the different parameters specifications of DVI?I have been looking for it all over..
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Altera_Forum
Honored Contributor II
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@primiano 

Is it possible to get the second version of your design. 

Had some problems with the DE2-70 and video capture. 

 

LG 

chgamauf
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Altera_Forum
Honored Contributor II
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nice work there.....

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