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TX sync header error insertion in Arria 10 GX

MamaSaru
New Contributor I
1,570 Views

Hi,
I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC.
I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable.
Packet Transmit and receive test is working good by viewing Rx stream port by Signal Tap.
For error insertion test, I have set "Enable TX sync header error insertion" option in the parameter editor, and I drove the tx_err_ins PHY input port.
But I have no Rx stream change after error insertion.
In my thought, by receiving corrupted sync header in the RX, the rx_enh_blk_lock output port would go low.
Do you have any method to confirm sync header error was inserted in the TX encoder?

In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
---
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
---
I can't find what "the error flag" is.

Thank you for any help.

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ZiYing_Intel
Employee
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Hi MamaSaru,

 

You can check sync header error through the status of the PCS sync header output by encode in PCS.

Besides that, the error flag here means the sync header error.

 

Best regards,

zying


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MamaSaru
New Contributor I
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Hi zying,

Thank you for your help.

>You can check sync header error through the status of the PCS sync header output by encode in PCS.

Can you teach me exact output signal name of the IP?

>Besides that, the error flag here means the sync header error.

Do you mean the error flag is the internal signal of the IP?

Regards,

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ZiYing_Intel
Employee
1,495 Views

Hi MamaSaru,


Do you still have any question about this issue?


Best regards,

zying


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ZiYing_Intel
Employee
1,445 Views

Hi,

 

You may check the sync header error status under the PCS> encode>sync_out in the simulation file.

 

The error flag means the sync header error. The CRC is inserted in the last 4 bytes of the frame (user data) by MAC block. Then, user data is sent to TX PCS, where 64B/66B operation is done. After this, the sync header error is added in the PCS block.

 

Best regards,

zying


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MamaSaru
New Contributor I
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ZiYing_Intel
Employee
1,405 Views

Hi,


I got send a picture. Caen you see it?


Best regards,

zying


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MamaSaru
New Contributor I
1,394 Views

No, I am sorry that no picture is displayed in your post.
I am reffering Intel Arria 10 Transceiver PHY User Guide 2023.09.15.
Pointing out somewhere from this doccument is helpfull.
If you need other document or file for explanation, please send me the file instead of the screenshot.

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ZiYing_Intel
Employee
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Hi,

 

You may check the sync header error status under the PCS> encode>sync_out in the your design simulation file.

 

Best regards,

zying

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MamaSaru
New Contributor I
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You misunderstand my intentions in the following two points.
1. I am not in simulation but in real A10 design.
2. I would like to check received syn header is corrupted at Rx side.

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ZiYing_Intel
Employee
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Hi,


Sorry for the delay in response. I am checking it with my internal team and will get back to you with findings.


Best regards,

zying


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ZiYing_Intel
Employee
1,111 Views

Hi MamaSaru,

 

Q1. Error Insertion on Sync Header

>> You are suggested to use C.0x089 bit[5] to insert error on sync header in the TX-path. Error happens once on every rising edge of C.0x089 bit[5] setting (0->1).

The "tx_err_ins" is control signal for Interlaken block, so it should not be used in this case.

For further information, you may refer to the Arria 10 Transceiver Register Map in the Arria 10 Transceiver PHY User Guide, Section 6.19, pg 575, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-register-map.html

 

Q2. How to check received syn header is corrupted at Rx side?

>> If the sync header of received 66B data is broken, it cannot be detected as data/control word. Then, it is consequently detected as CRC error and it may be dropped and identified CRC error or frame error.

It would be reflected to receiver statistics counter.

You can read receiver statistics counter registers.

 

Best regards,

zying


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MamaSaru
New Contributor I
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Hi zying,


For Q1:
I could find sh_err bit in the Extended Register Map as you suggested.
But I have no register access path for the register because I do not need to reconfigure the PHY.
In my opinion, adding the AND gate after the sh_err register bit is good for user in case that header error insertion logic is kicked by the rising edge of the sh_err register bit.
The tx_err_ins signal is usable with "Enable KR-FEC TX error insertion" option for FEC block.
The same usability of the tx_err_ins signal would be expected for 64b/66b encoder block.
I have to give it away the sync header error insertion test for now.

 

For Q2:
OK, I understand.

Thank you for you help.


My last question:
---
In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
---
What "error flag" is in this description?

 

MamaSaru

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ZiYing_Intel
Employee
1,054 Views

Hi MamaSaru,


The error flag means the sync header error. The CRC is inserted in the last 4 bytes of the frame (user data) by MAC block. Then, user data is sent to TX PCS, where 64B/66B operation is done. After this, the sync header error is added in the PCS block.


Best regards,

zying


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MamaSaru
New Contributor I
1,038 Views

zying,

I am sorry that I totally don't understand your explanation.
I will try to make my question more clear.

From description of Table 24, Two conditions should be realized to insert sync header error:
1. error insertion is enabled
I am very clear that this condition is realized by setting "Enable TX sync header error insertion" GUI check box on.
2. the error flag is set
I mean what is the error flag?

Regards,
MamaSaru

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ZiYing_Intel
Employee
948 Views

Hi MamaSaru,


After some discussion with our team, the error flag in the user guide maybe means "rising edge of C.0x089 bit[5] setting (0->1)."


Best regards,

zying



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MamaSaru
New Contributor I
935 Views

Hi,

By reading the section 6.19 of the user guide, It said that rewriting individual register is not recommended.

Besides, I have investigated where "Enable TX sync header error insertion" GUI setting contribute to the register map by comparing generated files under setting on and off.

I compared below files:
altera_xcvr_native_a10_reconfig_parameters.h
altera_xcvr_native_a10_reconfig_parameters.mif
altera_xcvr_native_a10_reconfig_parameters.sv

 

I have found that "Enable TX sync header error insertion" GUI setting contributes to "C.0x089 bit[5]".

According to your answer, "the error flag" comes from register "C.0x089 bit[5]" for condition 2 and "error insertion is enabled" also comes from register "C.0x089 bit[5]" for condition 1.
This explanation is not regal.

 

I think that the AND gate should be located output of the register "C.0x089 bit[5]".
I attached the rough drawing.

 

Regards,

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ZiYing_Intel
Employee
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Hi MamaSaru,

 

For further information, you may refer to its block diagram. Hope the attached image was useful to you.

 

Best regards,

zying

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MamaSaru
New Contributor I
899 Views

zying,
I understand the current inplementation of header error insertion function.
My intention is modification request to drive exposed signal like tx_err_ins for error insertion without using individual register modification.
This makes this function usable and match with current explanation on the user guide (two condition needed for insertion).
Please tell development team my request.
regards,
MamaSaru

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ZiYing_Intel
Employee
865 Views

Hi MamaSaru,


Sorry to tell you that we can't simply do modification on your design since we do not know your design requirement.


But according to your feedback, I have tell your request to development team for the enhancement design purpose. For the purpose of to drive exposed signal like tx_err_ins for error insertion without using individual register modification. This makes this function usable and match with current explanation on the user guide (two condition needed for insertion).


Best regards,

zying



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ZiYing_Intel
Employee
796 Views

Hi MamaSaru,


I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Best regards,

zying


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