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Test Pattern Generator -> Clocked Video Output with Altera NEEK

Altera_Forum
Honored Contributor I
1,417 Views

I have an Altera FPGA NEEK and I want to use the following VIP cores setup: CVI(Clocked Video Input) -> SCL(Scaler) -> FB(Frame Buffer) -> CVO(Clocked Video Output). 

This gives me a screen with vertical white stripes. 

 

Now I want to test it as minimal as possible, to see where the problem is. 

I want to use a Test Pattern Generator to see if the CVO core works. 

TPG -> CVO. What I get now is a black screen, without the white vertical lines. 

My question is, does the standard TPG from the VIP cores generates the color bars automatically? In other words: can I use TPG->CVO, without having to use a Nios II Processor to create the color bars with C program software code?
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6 Replies
Altera_Forum
Honored Contributor I
210 Views

In the latest documentation for Test Pattern Generator II IP Core, they included a screenshot of the test image. 

See https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_vip.pdf
Altera_Forum
Honored Contributor I
210 Views

I have seen it and read it, but I can't really understand if you MUST USE the Nios II Processor to generate the color bars with C software code.

Altera_Forum
Honored Contributor I
210 Views

NIOS software is not involved at all in generating the color bar pattern. 

 

The only way software can alter the pattern is if you have selected the uniform background output test pattern, and then change the R/G/B registers to alter the displayed color.
Altera_Forum
Honored Contributor I
210 Views

How do I connect CVO to SGDMA? 

 

I followed the System Architecture Tutorial of PictureViewer and have something working where it takes pictures from a SD card and using the following IP Cores (SGDMA->TimingAdapter->FIFO->TimingAdapter->FormatAdapter->PixelConverter->FormatAdapter->VideoSyncGenerator) to load the pictures on the LCD screen of my NEEK. 

 

There is no connection dot for a TPG or CVO to connect to the SGDMA. Am I missing another IP Core?
Altera_Forum
Honored Contributor I
210 Views

Found the solution. Thanks for your help ted Altera Guru! 

 

TPG->TimingAdapter->VideoSyncGenerator works, but the screen keeps blinking. 

Fixed this by using the VIP core ClockedVideoOutput: TPG->CVO and then set the lcd_video_interface values in Verilog .v. 

 

Now I have color bars on my Altera NEEK's screen!
Altera_Forum
Honored Contributor I
210 Views

 

--- Quote Start ---  

Found the solution. Thanks for your help ted Altera Guru! 

 

TPG->TimingAdapter->VideoSyncGenerator works, but the screen keeps blinking. 

Fixed this by using the VIP core ClockedVideoOutput: TPG->CVO and then set the lcd_video_interface values in Verilog .v. 

 

Now I have color bars on my Altera NEEK's screen! 

--- Quote End ---  

 

 

What filename or values did you use?
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