Dear all,I use the burst read master of Avalon MM templates in the Qsys and create the burst read master, clock crossing bridge and DDR2 controller UniPHY. The DDR2 controller UniPHY has 64 bit of data width, half rate of interface, 400MHz of the memory clock and 50Mhz of PLL. The settings of the clock crossing bridge and burst read master are shown as attached files. In the verilog file, I use a button to generate a pulse trigger signal and the pulse signal is used to trigger the "control_go" signal of the burst read master to high. After the trigger, the "control_done" signal will be low and the "read_buffer" (from FIFO) signal will be asserted as "data_available" signal is high. But the "control_done" signal does not go to "high" anymore, even the "data_available" signal to low. In additional remark, the "control_done" signal does not go to "high", because the "reads_pending" signal of the burst read master can not be decreased. The reason may be the DDR2 controller does not send the "write request" signal to the FIFO. So, how do I fix the problem? thanks. ps. I hope my description is clear. 11/25Update: When I removed the clock crossing bridge, the "reads_pending" signal of the burst read master can be decreased. But there are more and more "reads_pending" signal generating during one time trigger. The "control_done" signal is still not going to "high", and the "control_go" signal keeps low. Anyone has the same problem?:cry: -Yu-Ta
I made a big mistake that the read length is too small (1 byte). And then I increase the read length to 4 bytes, the burst read master can work.But it's still something wrong. Some read base address can not work after the trigger. Therefore, I supposed the aligned address is the key point. Does anyone have information about the aligned address of readout from DDR2 in the EP4SGX230(DE4)? I will appreciate your supports.