Timing Model for Stratix IV DDR3 Controller UniPhy IP - Hyperlynx

[Digital_Mike]

Hi,

I am trying to Verify our "DDR3 SDRAM Controller with UniPHY Intel FPGA IP" Board setting parameters and am using Hyperlynx to in an effort to get these Board parameters.

While using Hyperlynx, I am going thru the Hyperlynx Timing Model Wizard in order to update the Timing Model for the Stratix IV device.  

Can someone send me a link to the Stratix IV timing diagrams for DDR3, or possibly have a Stratix IV timing Model (DDR3*.v) file that I can import into this wizard? I'm not able to find the timing characteristics anywhere.

Thanks

Mike