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Honored Contributor I
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Timing problem related to ALT4GXB

Hi, 

 

I thought I had a pretty stable communication using ALT4GXB, but with more logic added into the design the communication become flaky. The byte stream I got on from the receiver in a loop back test in some compiles will be different from the byte stream I sent to the transmitter. In the debugging process I found that even when the only thing changed in a compile is the signaltap file, the result may change. If we strip down the logic the result will become stable again between compiles. But, we are using less than 30% of the resource even with all the logic added in so far.  

 

I do have some timing violations with the design, but they are all recovery time violations related to some FIFO in a Avalon clock crossing bridge in a SOPC core. If I take the SOPC core off the design, the loopback test runs stable. 

 

I wasn't planning on resolving those time violations because the Avalon clock crossing bridge are an IP from Altera. But should I? Or are there any timing constraint I can add for the ALT4GXB to constraint the design better? 

 

Any advice would be very much appreciated. 

 

Thanks, 

Hua
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