I'm using the Tri-Speed Ethernet IP on an Arria V FPGA.
The core has a 16 bit wide data Avalon MM Lite bus that allows access to internal registers.
However, some registers are 32 bits wide ( not 16 as the Avalon bus width ).
For example: "Command_Config Register" at page 85 :
The register address is 0x2 and it's 32 bits wide.
I assume that if I access address 0x2 over the Avalon bus I'd get bits 15:0.
How can I access bits 31:16 ?
If you look at TSE user guide doc (table 56, page 108), TSE MAC register Avalon bus interface is 32 bits width wide data bus.
May I know where do you see 16 bits Avalon bus on TSE IP ?
Your understanding is correct.
MAC reg address width is 32 bits but PCS reg address width is only 16 bits.
You can refer to TSE user guide doc for the reg control detail.
- Chapter 5.1 - MAC config reg space
- Chapter 5.2 - PCS config reg space
For your case, you just need to refer to chapter 5.2.
If you configured TSE IP with "PCS function" only, of course MAC function access will be disable as we won't expect user to use TSE MAC function anymore since you didn't initiate MAC function in the first place, right ? :)
Just making sure...
I was thinking that perhaps the MAC section has registers shared by the PCS function that must be configured as well.
I'm referring to section 5.3.2 ( page 103 ) of the user guide:
In my use case the core acts as an SGMII bridge - no MAC functionality if required.
So in my case only steps 1 & 2 are necessary ?
1.External PHY Initialization using MDIO
2.PCS Configuration Register Initialization