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SKon1
Novice
146 Views

Tri-Speed Ethernet IP - accessing "Command_Config Register"

Hello,

 

I'm using the Tri-Speed Ethernet IP on an Arria V FPGA.

The core has a 16 bit wide data Avalon MM Lite bus that allows access to internal registers.

However, some registers are 32 bits wide ( not 16 as the Avalon bus width ).

For example: "Command_Config Register" at page 85 :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf 

 

The register address is 0x2 and it's 32 bits wide.

I assume that if I access address 0x2 over the Avalon bus I'd get bits 15:0.

How can I access bits 31:16 ?

 

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8 Replies
Deshi_Intel
Moderator
109 Views

Hi,

 

If you look at TSE user guide doc (table 56, page 108), TSE MAC register Avalon bus interface is 32 bits width wide data bus.

 

May I know where do you see 16 bits Avalon bus on TSE IP ?

 

Thanks.

 

Regards,

dlim

SKon1
Novice
109 Views

That's the width of the Quartus generated HDL component.

Can it be because I have the core set to PCS only ?

 

Deshi_Intel
Moderator
109 Views

HI,

 

Your understanding is correct.

 

MAC reg address width is 32 bits but PCS reg address width is only 16 bits.

 

You can refer to TSE user guide doc for the reg control detail.

  • Chapter 5.1 - MAC config reg space
  • Chapter 5.2 - PCS config reg space

 

For your case, you just need to refer to chapter 5.2.

 

Thanks.

 

Regards,

dlim

SKon1
Novice
109 Views

So if configure the core as "PCS Only" - the MAC registers are essentially inaccessible ?

Deshi_Intel
Moderator
109 Views

HI,

 

If you configured TSE IP with "PCS function" only, of course MAC function access will be disable as we won't expect user to use TSE MAC function anymore since you didn't initiate MAC function in the first place, right ? :)

 

Thanks.

 

Regards,

dlim

SKon1
Novice
109 Views

Just making sure...

I was thinking that perhaps the MAC section has registers shared by the PCS function that must be configured as well.

I'm referring to section 5.3.2 ( page 103 ) of the user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

 

In my use case the core acts as an SGMII bridge - no MAC functionality if required.

So in my case only steps 1 & 2 are necessary ?

1.External PHY Initialization using MDIO

2.PCS Configuration Register Initialization

Deshi_Intel
Moderator
109 Views

HI,

 

Correct. You only need to perform step 1 and step 2.

 

I presume you had your own MAC IP where you will initialize your MAC IP separately.

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
107 Views

HI,


I hope I have cleared your doubt in my earlier feedback.


For now, I am setting this case to closure.


Thanks.


Regards,

dlim


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