FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Triple Rate SDI question

Altera_Forum
Honored Contributor II
741 Views

I have question on Tripler rate SDI reference clock frequency. So far I am only using the 148.5MHZ , and it seems to work for all formats SD/HD/3G.  

It is generated from an external 27MHZ oscillator via the PLL. 

 

On the SDI userguide, there is also a 148.35MHZ reference clock listed for triple rate SDI , and it does not really explain the reason behind it.  

 

Could somebody please tell me why/when such frequecy clock needed? 

 

Thanks in advance, 

 

 

JIMMY
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
64 Views

Hello Jimmy, 

 

I do not know if you are talking about SDI input (receiver) or SDI output (transmitter)? 

 

In the receiver the reference clock (rx_serial_refclk) is only need for training the receiver PLL it does not need to be frequency locked to the input data. 

So you can use either 148.5MHz or 148.35MHz. 

 

In the transmitter the reference clock (tx_serial_refclk) is used to generate the serial output stream so it must be locked to the video frequency 148.5MHz for 60Hz or 148.35MHz for 59.94Hz. 

 

BR, 

Reuven
Altera_Forum
Honored Contributor II
64 Views

Thank you very much, 

 

JIMMY
Reply